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| TOSHIBA Original CMOS 16-Bit Microcontroller TLCS-900/L1 Series TMP91C025FG Semiconductor Company Preface Thank you very much for making use of Toshiba microcomputer LSIs. Before use this LSI, refer the section, "Points of Note and Restrictions". Especially, take care below cautions. **CAUTION** How to release the HALT mode Usually, interrupts can release all halts status. However, the interrupts = (INT0 to INT3, INTRTC, INTALM0 to INTALM4, INTKEY), which can release the HALT mode may not be able to do so if they are input during the period CPU is shifting to the HALT mode (for about 5 clocks of fFPH) with IDLE1 or STOP mode (IDLE2 is not applicable to this case). (In this case, an interrupt request is kept on hold internally.) If another interrupt is generated after it has shifted to HALT mode completely, halt status can be released without difficultly. The priority of this interrupt is compare with that of the interrupt kept on hold internally, and the interrupt with higher priority is handled first followed by the other interrupt. TMP91C025 CMOS 16-Bit Microcontrollers TMP91C025FG/JTMP91C025-S 1. Outline and Features TMP91C025 is a high-speed 16-bit microcontroller designed for the control of various mid- to large-scale equipment. TMP91C025FG comes in a 100-pin flat package. JTMP91C025-S comes in a 100-pad chip. Listed below are the features. (1) High-speed 16-bit CPU (900/L1 CPU) * * * * * Instruction mnemonics are upward-compatible with TLCS-90 16 Mbytes of linear address space General-purpose registers and register banks 16-bit multiplication and division instructions; bit transfer and arithmetic instructions Micro DMA: 4 channels (444 ns/ 2 bytes at 36 MHz) (2) Minimum instruction execution time: 111 ns (at 36 MHz) RESTRICTIONS ON PRODUCT USE * The information contained herein is subject to change without notice. 021023_D 070208EBP * TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc. 021023_A * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. 021023_B * The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties. 021023_C * The products described in this document are subject to foreign exchange and foreign trade control laws. 060925_E * For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 030619_S 91C025-1 2007-02-28 TMP91C025 (3) Built-in RAM: None Built-in ROM: None (4) External memory expansion * * * Expandable up to 104 Mbytes (Shared program/data area) Can simultaneously support 8-/16-bit width external data bus ... Dynamic data bus sizing Separate bus system (5) 8-bit timers: 4 channels (6) General-purpose serial interface: 2 channels * * * * UART/Synchronous mode: 2 channels IrDA Ver.1.0 (115.2 kbps) mode selectable: 1 channel Adapt to both shift register type and built-in RAM type LCD driver Based on TC8521A (7) LCD controller (8) Timer for real-time clock (RTC) (9) Key-on wakeup (Interrupt key input) (10) 10-bit AD converter: 4 channels (11) Touch screen interface * Available to reduce external components (12) Watchdog timer (13) Melody/alarm generator * * * Melody: Output of clock 4 to 5461 Hz Alarm: Output of the 8 kinds of alarm pattern Output of the 5 kinds of interval interrupt (14) Chip select/wait controller: 4 channels (15) MMU * * * * Expandable up to 104 Mbytes 9 CPU interrupts: Software interrupt instruction and illegal instruction 23 internal interrupts: 7 priority levels are selectable 5 external interrupts: 7 priority levels are selectable (among 4 interrupts are selectable edge mode) (16) Interrupts: 37 interrupt (17) Input/output ports: 49 pins (Except Data bus (8bit), Address bus (24bit) and RD pin) (18) Standby function Three HALT modes: IDLE2 (Programmable), IDLE1 and STOP (19) Hardware standby function (Power save function) 91C025-2 2007-02-28 TMP91C025 (20) Triple-clock controller * * * * * * * Clock doubler (DFM) circuit is inside Clock gear function: Select a high-frequency clock fc/1 to fc/16 SLOW mode (fs = 32.768 kHz) VCC = 3.0 V to 3.6 V (fc max = 36 MHz) VCC = 2.7 V to 3.6 V (fc max = 27 MHz) VCC = 2.4 V to 3.6 V (fc max = 16 MHz) 100-pin QFP: P-LQFP100-1414-0.50F, chip form supply also available. For details, contact your local Toshiba sales representative. (21) Operating voltage (22) Package 91C025-3 2007-02-28 TMP91C025 DVCC [2] DVSS [2] AN2/MX (P82) AN3/MY/ ADTRG (P83) AN0, AN1 (P80, P81) AVCC, AVSS VREFH, VREFL TXD0 (PC0) RXD0 (PC1) SCLK0/ CTS0 (PC2) TXD1 (PC3) RXD1 (PC4) SCLK1/ CTS1 (PC5) CPU (TLCS-900/L1) 10-bit 4-channel AD converter XWA XBC XDE XHL XIX XIY XIZ XSP WA BC DE HL IX IY IZ SP 32 bits SR F PC H-OSC Clock gear, Clock doubler L-OSC X1 X2 EMU0 EMU1 XT1 XT2 RESET SIO/UART/IrDA (SIO0) SIO/UART (SIO1) Touch screen I/F (TSI) 8-bit timer (TMRA0) 8-bit timer (TMRA1) 8-bit timer (TMRA2) AM0 AM1 D0 to D7 A0 to A7 A8 to A15 PX/INT2 (PB5) PY/INT3 (PB6) WDT (Watchdog timer) Port 1 Port 2 P10 to P17 (D8 to D15) P20 to P27 (A16 to A23) RD WR TA0IN/INT1 (PB4) TA1OUT/KO1 (PA1) Port 5 Port Z HWR (PZ2) WAIT (P56) TA3OUT/KO2 (PA2) 8-bit timer (TMRA3) Port 6 CS/WAIT controller (4 blocks) R/ W / SRWR (PZ3) CS0 to CS3 , CS2A (P60 to P63) Port 8 Port 9 Port A Port B Port C Port D D1BSCP (PD0) D2BLP (PD1) D3BFR (PD2) DLEBCD (PD3) DOFFB (PD4) LCD controller EA24/ CS2B / SRLB (P64) MMU EA25/ CS2C / SRUB (P65) Interrupt controller INT0 ( PS ) INT0 to INT3 (PB3 to PB6) KI0 to KI7 (P90 to P97) KO0/ ALARM / MLDALM (PA0) KO1/TA1OUT (PA1) KO2/TA3OUT (PA2) KO3 (PA3) MLDALM (PD7) Keyboard I/F Melody/ alarm out RTC ALARM / MLDALM /KO0 (PA0) ( ): Initial function after reset Figure 1.1 TMP91C025 Block Diagram 91C025-4 2007-02-28 TMP91C025 2. Pin Assignment and Pin Functions The assignment of input/output pins for the TMP91C025, their names and functions are as follows: 2.1 Pin Assignment Diagram Figure 2.1.1 shows the pin assignment of the TMP91C025FG. 95 90 85 VREFL AVSS AVCC P80/AN0 P81/AN1 P82/AN2/MX P83/AN3/ ADTRG /MY PB5/PX/INT2 PB6/PY/INT3 P90/KI0 P91/KI1 P92/KI2 P93/KI3 P94/KI4 P95/KI5 P96/KI6 P97/KI7 PA0/KO0/ ALARM / MLDALM PA1/KO1/TA1OUT PA2/KO2/TA3OUT PA3/KO3/SCOUT PC0/TXD0 PC1/RXD1 AM0 DVCC1 1 100 80 VREFH PB3/INT0/PS PD7/MLDALM P65/EA25/CS2C/SRUB P64/EA24/CS2B/SRLB P63/CS3 P62/CS2/CS2A P61/CS1 P60/CS0 P56/WAIT PZ3/R/W/SRWR PZ2/HWR WR RD A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 75 5 70 10 TMP91C025FG QFP100 Top view 15 65 60 20 55 25 30 35 40 45 50 A11 A12 A13 A14 A15 P20/A16 P21/A17 P22/A18 P23/A19 P24/A20 P25/A21 DVCC2 PB4/INT1/TA0IN DVSS2 P26/A22 P27/A23 P17/D15 P16/D14 P15/D13 P14/D12 P13/D11 P12/D10 P11/D9 P10/D8 D7 Figure 2.1.1 Pin Assignment Diagram (100-pin QFP) X2 DVSS1 X1 AM1 RESET XT1 XT2 EMU0 EMU1 PC2/SCLK0/CTS0 PC3/TXD1 PC4/RXD1 PC5/SCLK1/CTS1 PD0/D1BSCP PD1/D2BLP PD2/D3BFR PD3/DLEBCD PD4/DOFFB D0 D1 D2 D3 D4 D5 D6 91C025-5 2007-02-28 TMP91C025 2.2 Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 PAD Layout (Chip size 4.58 mm x 4.63 mm) Name VREFL AVSS AVCC P80 P81 P82 P83 PB5 PB6 P90 P91 P92 P93 P94 P95 P96 P97 PA0 PA1 PA2 PA3 PC0 PC1 AM0 DVCC1 X2 DVSS1 X1 AM1 RESET Unit (m) Name D0 D1 D2 D3 D4 D5 D6 D7 P10 P11 P12 P13 P14 P15 P16 P17 P27 P26 DVSS2 PB4 DVCC2 P25 P24 P23 P22 P21 P20 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 X Point -2151 -2151 -2151 -2151 -2151 -2151 -2151 -2151 -2151 -2151 -2151 -2151 -2151 -2151 -2151 -2151 -2151 -2151 -2151 -2151 -2151 -2151 -2151 -2151 -2151 -1603 -1438 -1273 -1147 -1022 -897 -649 -524 -398 -273 -148 -23 101 226 352 477 602 727 Y Point 1627 1502 1376 1251 1126 1001 876 751 625 336 211 86 -38 -163 -289 -414 -539 -664 -789 -914 -1040 -1165 -1290 -1415 -1636 -2175 -2175 -2175 -2175 -2175 -2175 -2175 -2175 -2175 -2175 -2175 -2175 -2175 -2175 -2175 -2175 -2175 -2175 Pin No. 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 X Point 852 977 1103 1228 1353 1478 1603 2151 2151 2151 2151 2151 2151 2151 2151 2151 2151 2151 2151 2151 2151 2151 2151 2151 2151 2151 2151 2151 2151 2151 2151 2151 1603 1477 1350 1224 1097 970 844 717 590 464 337 Y Point -2175 -2175 -2175 -2175 -2175 -2175 -2175 -1636 -1490 -1359 -1228 -1096 -965 -834 -703 -571 -440 -309 -153 2 158 315 446 577 708 839 971 1102 1233 1364 1495 1627 2175 2175 2175 2175 2175 2175 2175 2175 2175 2175 2175 Pin No. 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Name RD WR X Point 210 83 -42 -169 -296 -421 -548 -674 -801 -926 -1051 -1177 -1302 -1606 Y Point 2175 2175 2175 2175 2175 2175 2175 2175 2175 2175 2175 2175 2175 2175 PZ2 PZ3 P56 P60 P61 P62 P63 P64 P65 PD7 PB3 VREFH XT1 XT2 EMU0 EMU1 PC2 PC3 PC4 PC5 PD0 PD1 PD2 PD3 PD4 91C025-6 2007-02-28 TMP91C025 2.3 Pin Names and Functions The names of the input/output pins and their functions are described below. Table 2.3.1 Pin Names and Functions (1/3) Pin Name D0 to D7 P10 to P17 D8 to D15 P20 to P27 A16 to A23 A8 to A15 A0 to A7 RD WR Number of Pins 8 8 I/O I/O I/O I/O Functions Data (lower): bits 0 to 7 of data bus Port 1: I/O port that allows I/O to be selected at the bit level (When used to the external 8bit bus) Data (upper): Bits 8 to15 of data bus Port 2: Output port Address: Bits 16 to 23 of address bus Address: Bits 8 to 15 of address bus Address: Bits 0 to 7 of address bus Read: Strobe signal for reading external memory Write: Strobe signal for writing data to pins D0 to D7 Port Z2: I/O port (with pull-up resistor) High Write: Strobe signal for writing data to pins D8 to D15 Port Z3: I/O port (with pull-up resistor) Read/Write: 1 represents read or dummy cycle; 0 represents write cycle. Write: Strobe signal for writing data to pins D0 to D15 for SRAM Port 56: I/O port (with pull-up resistor) Wait: Pin used to request CPU bus wait Port 60:Output port Chip select 0: Outputs 0 when address is within specified address area. Port 61:Output port Chip select 1: Outputs 0 when address is within specified address area Port 62: Output port Chip select 2: Outputs 0 when address is within specified address area Expand chip select: 2A: Outputs 0 when address is within specified address area Port 63:Output port Chip select 3: Outputs 0 when address is within specified address area Port 64: Output port Chip select 24: Outputs 0 when address is within specified address area Expand chip select: 2B: Outputs 0 when address is within specified address area Low byte enable for SRAM Port 65: Output port Chip select 25: Outputs 0 when address is within specified address area Expand chip select: 2C: Outputs 0 when address is within specified address area High byte enable for SRAM 8 8 8 1 1 1 1 Output Output Output Output Output Output I/O Output I/O Output Output PZ2 HWR PZ3 R/ W SRWR P56 WAIT 1 1 1 1 I/O Input Output Output Output Output Output Output Output P60 CS0 P61 CS1 P62 CS2 CS2A P63 CS3 1 1 Output Output Output Output Output Output P64 EA24 CS2B SRLB P65 EA25 CS2C 1 Output Output Output Output SRUB 91C025-7 2007-02-28 TMP91C025 Table 2.3.2 Pin Names and Functions (2/3) Pin Name P80 to P81 AN0 to AN1 P82 AN2 MX P83 AN3 ADTRG Number of Pins 2 1 I/O Input Input Input Input Input Functions Port 80 to 81 port: Pin used to input ports Analog input 0 to 1: Pin used to input to AD converter Port 82 port: Pin used to input ports Analog input 2: Pin used to input to AD converter X-Minus: Pin connected to X- for touch screen panel Port 83 port: Pin used to input ports Analog input 3: Pin used to input to AD converter AD trigger: Signal used to request AD start Y-Minus: Pin connected to Y- for touch screen panel Port: 90 to 97 port: Pin used to input ports Key input 0 to 7: Pin used of key-on wakeup 0 to 7 (Schmitt input, with pull-up resistor) Port: A0 port: Pin used to output ports Key output 0: Pin used of key-scan strobe 0 RTC alarm output pin Melody/alarm output pin (Inverted) Port: A1 port: Pin used to output ports Key output 1: Pin used of key-scan strobe 1 8-bit timer 1 output: Timer 0 input or timer 1 output Port: A2 port: Pin used to output ports Key output 2: Pin used of key-scan strobe 2 8-bit timer 3 output: Timer 2 input or timer 3 output Port: A3 port: Pin used to output ports Key output 3: Pin used of key-scan strobe 3 System clock output: Output fFPH clock Port B3: I/O port Interrupt request pin0: Interrupt request with programmable level/rising edge Power save: Pin used as input pin for H/W standby mode Port B4: I/O port Interrupt request pin1: Interrupt request with programmable rising/falling edge 8-bit timer 0 input: Timer 0 input Port B5: Input port Interrupt request pin2: Interrupt request with programmable rising/falling edge X-Plus: Pin connected to X+ for touch screen panel Port B6: Input port Interrupt request pin3: Interrupt request with programmable rising/falling edge Y-Plus: Pin connected to Y+ for touch screen panel Port C0: I/O port Serial 0 send data: Open-drain output pin by programmable Port C1: I/O port Serial 0 receive data 1 Input Input Input Input MY P90 to P97 KI0 to KI7 PA0 KO0 ALARM MLDALM 8 Input Input 1 Output Output Output Output PA1 KO1 TA1OUT PA2 KO2 TA3OUT PA3 KO3 SCOUT PB3 INT0 PS 1 Output Output Output 1 Output Output Output 1 Output Output Output 1 I/O Input Input PB4 INT1 TA0IN PB5 INT2 PX PB6 INT3 PY PC0 TXD0 PC1 RXD0 1 I/O Input Input 1 Input Input Output 1 Input Input Output 1 1 I/O Output I/O Output Note: After reset, input "1" to PB3 (INT0, PS )-pin, because it is worked as PS input pin. 91C025-8 2007-02-28 TMP91C025 Table 2.3.3 Pin Names and Functions. (3/3) Pin Name PC2 SCLK0 CTS0 Number of Pins 1 I/O I/O I/O Input Functions Port C2: I/O port (with pull-up resistor) Serial clock I/O 0 Serial data send enable 0 (Clear to send) Port C3: I/O port Serial send data 1 Open-drain output pin by programmable Port C4: I/O port Serial receive data 1 Port C5: I/O port (with pull-up resistor) Serial clock I/O 1 Serial data send enable 1 (Clear to send) Low-frequency oscillator connecting pin Low-frequency oscillator connecting pin Port D0: Output port LCD controller output pin Port D1: Output port LCD controller output pin Port D2: Output port LCD controller output pin Port D3: Output port LCD controller output pin Port D4: Output port LCD controller output pin Port D7: Output port Melody/alarm output pin Operation mode: Fixed to AM1 = 0, AM0 = 1 16-bit external bus or 8-/16-bit dynamic sizing. Fixed to AM1 = 0, AM0 = 0 8-bit external bus fixed. PC3 TXD1 PC4 RXD1 PC5 SCLK1 CTS1 1 I/O Output 1 1 I/O Input I/O I/O Input XT1 XT2 PD0 D1BSCP PD1 D2BLP PD2 D3BFR PD3 DLEBCD PD4 DOFFB PD7 MLDALM AM0 to AM1 1 1 1 1 1 1 1 1 2 Input Output Output Output Output Output Output Output Output Output Output Output Output Output Input EMU0 EMU1 RESET 1 1 1 1 1 1 1 2 2 2 Output Output Input Input Input Open pin Open pin Reset: initializes TMP91C025. (with pull-up resistor) Pin for reference voltage input to AD converter (H) Pin for reference voltage input to AD converter (L) Power supply pin for AD converter GND pin for AD converter (0 V) VREFH VREFL AVCC AVSS X1, X2 DVCC DVSS I/O High-frequency oscillator connection pins Power supply pins (All VCC pins should be connected with the power supply pin.) GND pins (0 V) (All pins should be connected with GND (0 V).) 91C025-9 2007-02-28 TMP91C025 3. Operation This following describes block by block the functions and operation of the TMP91C025. Notes and restrictions for eatch book are outlined in 6, precautions and restrictions at the end of this manual. 3.1 CPU The TMP91C025 incorporates a high-performance 16-bit CPU (the 900/L1-CPU). For CPU operation, see the TLCS-900/L1 CPU. The following describe the unique function of the CPU used in the TMP91C025; these functions are not covered in the TLCS-900/L1 CPU section. 3.1.1 Reset When resetting the TMP91C025 microcontroller, ensure that the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then hold the RESET input to low level at least for 10 system clocks (9 s at 36 MHz). Thus, when turn on the switch, be set to the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then hold the RESET input to low level at least for 10 system clocks. Clock gear is initialized 1/16 mode by reset operation. It means that the system clock mode fSYS is set to fc/32(= fc/16 x 1/2). When the reset is accept, the CPU: * Sets as follows the program counter (PC) in accordance with the reset vector stored at address FFFF00H to FFFF02H: PC<0:7> PC<15:8> PC<23:16> * * * * Value at FFFF00H address Value at FFFF01H address Value at FFFF02H address Sets the stack pointer (XSP) to 100H. Sets bits When reset is released,the CPU starts executing instructions in accordance with the program counter settings. CPU internal registers not mentioned above do not change when the reset is released. When the reset is accepted, the CPU sets internal I/O, ports, and other pins as follows. * * Initializes the internal I/O registers. Sets the port pins, including the pins that also act as internal I/O, to general-purpose input or output port mode. Note: The CPU internal register (Except to PC, SR, XSP) do not change by resetting. Figure 3.1.1 is a reset timing chart of the TMP91C025. 91C025-10 2007-02-28 fFPH Sampling Sampling RESET A23 to A0 0FFFF00H CS0, CS1, CS3 CS2 D0 to D15 Data-in Data-in Read Figure 3.1.1 Reset Timing Chart 91C025-11 (PZ2 input mode) RD (After reset released, starting 2 wait read cycle) D0 to D15 Data-out Write WR HWR XT1, XT2 TMP91C025 2007-02-28 Pull-up (Internal) High-Z TMP91C025 3.2 Memory Map Figure 3.2.1 is a memory map of the TMP91C025. 000000H Internal I/O (4 Kbytes) 000100H 000FE0H 001000H (Note) 64-Kbyte area (nn) Direct area (n) 010000H External memory 16-Mbyte area (R) (-R) (R+) (R + R8/16) (R + d8/16) (nnn) FFFF00H FFFFFFH Vector table (256 bytes) ( = Internal area) Figure 3.2.1 Memory Map Note: Address 000FE0H to 000FEFH is assigned for the external memory area of built-in RAM type LCD driver. Address 000FF0H to 000FFFH is assingned for the external memory area as reserved. 91C025-12 2007-02-28 TMP91C025 3.3 Triple Clock Function and Standby Function TMP91C025 contains a clock gear, clock doubler (DFM), standby controller and noise-reduction circuit. It is used for low-power and low-noise systems. This chapter is organized as follows: 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.3.6 3.3.7 Block Diagram of System Clock SFRs System Clock Controller Prescaler Clock Controller Clock Doubler (DFM) Noise reducing Circuit Standby Controller 91C025-13 2007-02-28 TMP91C025 The clock operating modes are as follows: (a) Single clock mode (X1, X2 pins only), (b) Dual clock mode (X1, X2, XT1 and XT2 pins) and (c) Triple clock mode (the X1, X2, XT1 and XT2 pins and DFM). Figure 3.3.1 shows a transition figure. Reset (fOSCH/32) IDLE2 mode (I/O operate) IDLE1 mode (Operate only oscillator) Instruction Interrupt Instruction Interrupt (a) Release reset NORMAL mode (fOSCH/Gear value/2) Instruction Interrupt STOP mode (Stops all circuits) Single clock mode transition figure Reset (fOSCH/32) IDLE2 mode (I/O operate) IDLE1 mode (Operate only oscillator) IDLE2 mode (I/O operate) IDLE1 mode (Operate only oscillator) Instruction Interrupt Instruction Interrupt Instruction Interrupt Instruction Interrupt (b) Release reset NORMAL mode (fOSCH/Gear value/2) Instruction Interrupt STOP mode (Stops all circuits) SLOW mode (fs/2) Dual clock mode transition figure Reset (fOSCH/32) IDLE2 mode (I/O operate) IDLE1 mode (Operate only oscillator) Instruction Interrupt Instruction Interrupt Release reset NORMAL mode (fOSCH/Gear value/2) Instruction (Note) IDLE2 mode (I/O operate) Instruction Interrupt NORMAL mode (4 x fOSCH/gear value/2) STOP mode (Stops all circuits) Instruction Instruction (Note) Instruction Interrupt Instruction SLOW mode (fs/2) Interrupt Instruction IDLE2 mode (I/O operate) IDLE1 mode (Operate only oscillator) IDLE1 mode Instruction (Operate oscillator and DFM) Interrupt Using DFM (c) Triple clock mode trasision figure Interrupt Note 1: It's prohibited to control DFM in SLOW mode when shifting from SLOW mode to NORMAL mode with use of DFM. DFM start up/stop/change write to DFMCR0 Figure 3.3.1 System Clock Block Diagram The clock frequency input from the X1 and X2 pins is called fc and the clock frequency input from the XT1 and XT2 pins is called fs. The clock frequency selected by SYSCR1 91C025-14 2007-02-28 TMP91C025 3.3.1 Block Diagram of System Clock SYSCR0 /2 /4 SYSCR0 /2 fc/2 fc/4 fc/8 fc/16 /8 /16 fSYS SYSCR0 SYSCR1 SYSCR1 Clock gear DFMCR0 fSYS TMRA0 to TMRA3 T0 Prescaler CPU Interrupt controller ADC SIO0 to SIO1 WDT Prescaler I/O ports TSI C/S WAIT controller RTC fs LCDC MLD/ALM Figure 3.3.2 Block Diagram of System Clock 91C025-15 2007-02-28 TMP91C025 3.3.2 SFRs 7 SYSCR0 (00E0H) Bit symbol Read/Write After reset Function Highfrequency 0: Stop 6 XTEN 1 Lowfrequency 0: Stop 5 RXEN 1 Highfrequency Low- 4 RXTEN 0 frequency 3 RSYSCK R/W 0 Selects clock after timer 2 WUEF 0 Warm-up 0: Write 1: Write start timer 0: Read end warm-up 1:Read do not end warm-up 1 PRCK1 0 00: fFPH 01: Reserved 11: Reserved 0 PRCK0 0 XEN 1 Select prescaler clock oscillator (fc) oscillator (fs) oscillator (fc) oscillator (fs) release of after release after release STOP mode of STOP mode 0: Stop 0: fc 1: fs 1: Oscillation 1: Oscillation of STOP (Note 1) mode 0: Stop Don't care 10: fc/16 1: Oscillation 1: Oscillation 7 SYSCR1 (00E1H) Bit symbol Read/Write After reset Function 6 5 4 3 SYSCK 0 Select system clock 0: fc 1: fs 2 GEAR2 R/W 1 000: fc 001: fc/2 010: fc/4 011: fc/8 100: fc/16 101: (Reserved) 110: (Reserved) 111: (Reserved) 1 GEAR1 0 0 GEAR0 0 Select gear value of high-frequency (fc) 7 SYSCR2 (00E2H) Bit symbol Read/Write After reset Function PSENV R/W 0 0: Power save mode enable 1: Disable (Note 2) 6 5 WUPTM1 R/W 1 Warm-up timer 00: Reserved 4 WUPTM0 R/W 0 3 HALTM1 R/W 1 HALT mode 00: Reserved 01: STOP mode 10: IDLE1 mode 11: IDLE2 mode 2 HALTM0 R/W 1 1 SELDRV R/W 0 0 DRVE R/W 0 Pin state control in STOP/IDLE1 mode 0: I/O off the state before halt 01: 28/inputted frequency 10: 214 11: 216 (Note 3) 1: Remains Note 1: Note 2: Note 3: By reset, low-frequency oscillator is enabled. When hard ware standby mode is entered, the meaning of SYSCR2 Figure 3.3.3 SFRs for System Clock 91C025-16 2007-02-28 TMP91C025 Symbol Name Address 7 ACT1 R/W 6 ACT0 R/W 0 5 DLUPFG R 0 4 DLUPTM R/W 0 Lock up Time 0: 212/fOSCH 1: 210/fOSCH 3 2 1 0 DFM DFMCR0 control register 0 E8H 0 DFM LUP select fFPH Lock up 00 STOP STOP fOSCH 01 RUN RUN fOSCH 10 RUN STOP fDFM 11 RUN STOP fOSCH D7 D6 R/W 0 D5 R/W 0 status Flag 0: End 1: Not end D4 R/W 1 D3 R/W 0 D2 R/W 0 D1 R/W 1 D0 R/W 1 DFMCR1 DFM control register 1 E9H R/W 0 DFM revision Input frequency 4 to 9 MHz (at 3.0 V to 3.6 V): write 0BH Input frequency 4 to 6.75 MHz (at 2.7 V to 3.6 V): write 0BH Figure 3.3.4 SFRs for DFM Limitation point on the use of DFM 1. It's prohibited to execute DFM enable/disable control in the SLOW mode (fs) (write to DFMCR0 LD LD (DFMCR0), C0H (DFMCR0), 00H ; ; Change the clock fDFM to fOSCH DFM stop 3. If you stop high-frequency oscillator during using DFM (DFMCR0 91C025-17 2007-02-28 TMP91C025 7 EMCCR0 (00E3H) Bit symbol Read/Write After reset Function 0: Off 1: On 6 R/W 0 LCDC source CLK 0: 32 kHz 1: TA3OUT 5 AHOLD R/W 0 Address hold 0: Disable 1: Enable (Note) 4 TA3MLDE R/W 0 Melody/alarm source clock 0: 32 kHz 1: TA3OUT 3 - R/W 0 Always write 0. 2 EXTIN R/W 0 1: External clock 1 DRVOSCH 0 DRVOSCL PROTECT TA3LCDE R 0 Protect flag R/W 1 fc oscillator driver ability 1: Normal 0: Weak R/W 1 fs oscillator driver ability 1: Normal 0: Weak EMCCR1 (00E4H) Bit symbol Read/Write After reset Function Switching the protect ON/OFF by write to following 1st-KEY, 2nd-KEY 1st-KEY: EMCCR1 = 5AH, EMCCR2 = A5H in succession write 2nd-KEY: EMCCR1 = A5H, EMCCR2 = 5AH in succession write EMCCR2 (00E5H) Bit symbol Read/Write After reset Function EMCCR3 (00E6H) Bit symbol Read/Write After reset Function ENFROM R/W 0 CS1A area detect control 0: Disable 1: Enable ENDROM R/W 0 CS2B-2C area detect control 0: Disable 1: Enable ENPROM R/W 0 CS2A area detect control 0: Disable 1: Enable FFLAG R/W 0 CS1A write operation flag DFLAG R/W 0 operation flag PFLAG R/W 0 operation flag When writing 0: Clear flag CS2B-2C write CS2A write When reading 0: Not written 1: Written Note1: When getting access to the logic address 000000H to 000FDFH, A0 to A23 holds the previous address of external access. Note2: In case restarting the oscillator in the stop oscillation state (e.g. Restart the oscillator in STOP mode), set EMCCR0 Figure 3.3.5 SFRs for Noise Reduction 91C025-18 2007-02-28 TMP91C025 3.3.3 System Clock Controller The system clock controller generates the system clock signal (fSYS) for the CPU core and internal I/O. It contains two oscillation circuits and a clock gear circuit for high-frequency (fc) operation. The register SYSCR1 01 (2 /frequency) 10 (2 /frequency) 11 (2 /frequency) 16 14 8 Change to NORMAL Mode 7.1 (s) 0.455 (ms) 1.820 (ms) Change to SLOW Mode 7.8 (ms) 500 (ms) 2000 (ms) at fOSCH = 36 MHz, fs = 32.768 kHz 91C025-19 2007-02-28 TMP91C025 (Example 1: Setting the clock) Changing from high-frequency (fc) to low-frequency (fs). SYSCR0 SYSCR1 SYSCR2 EQU EQU EQU LD SET SET WUP: BIT JR SET RES 00E0H 00E1H 00E2H (SYSCR2), - X11 - - - - B 6, (SYSCR0) 2, (SYSCR0) 2, (SYSCR0) NZ, WUP 3, (SYSCR1) 7, (SYSCR0) ; ; ; ; ; ; ; Sets warm-up time to 2 /fs. Enables low-frequency oscillation. Clears and starts warm-up timer. Detects stopping of warm-up timer. Changes fSYS from fc to fs. Disables high-frequency oscillation. 16 x: Don't care -: No change Warm-up timer End of warm-up timer Counts up by fSYS Counts up by fs fc fs Enables low-frequency Clears and starts warm-up timer Chages fSYS from fc to fs End of warm-up timer Disables high-frequency 91C025-20 2007-02-28 TMP91C025 (Example 2: Setting the clock) Changing from low-frequency (fs) to high-frequency (fc). SYSCR0 SYSCR1 SYSCR2 EQU EQU EQU LD SET SET WUP: BIT JR RES RES 00E0H 00E1H 00E2H (SYSCR2), -X10 - - - - B 7, (SYSCR0) 2, (SYSCR0) 2, (SYSCR0) NZ, WUP 3, (SYSCR1) 6, (SYSCR0) ; ; ; ; ; ; ; Sets warm-up time to 2 /fc. Enables high-frequency oscillation. Clears and starts warm-up timer. Detects stopping of warm-up timer. Changes fSYS from fs to fc. Disables low-frequency oscillation. 14 x: Don't care -: No change Warm-up timer End of warm-up timer Counts up by fSYS Counts up by fOSCH fs fc Enables high-frequency Clears and starts warm-up timer Chages fSYS from fs to fc End of warm-up timer Disables low-frequency 91C025-21 2007-02-28 TMP91C025 (2) Clock gear controller When the high-frequency clock fc is selected by setting SYSCR1 SYSCR1 EQU LD 00E1H (SYSCR1), XXXX0000B ; Changes fSYS to fc/2. X: Don't care (High-speed clock gear changing) To change the clock gear, write the register value to the SYSCR1 SYSCR1 EQU LD LD 00E1H (SYSCR1), XXXX0001B (DUMMY), 00H ; ; Changes fSYS to fc/4. Dummy instruction Instruction to be executed after clock gear has changed (3) Internal clock output pin An internal clock fFPH can be output to the PA3/SCOUT pin. By setting "1" to the PAFC2 91C025-22 2007-02-28 TMP91C025 3.3.4 Prescaler Clock Controller For the internal I/O (TMRA01 to TMRA23, SIO0 to SIO1) there is a prescaler which can divide the clock. The T0 clock input to the prescaler is either the clock fFPH divided by 4 or the clock fc/16 divided by 4. The setting of the SYSCR0 3.3.5 Clock Doubler (DFM) DFM outputs the fDFM clock signal, which is four times as fast as fOSCH. It can use the low-frequency oscillator, even though the internal clock is high frequency . A reset initializes DFM to stop status, setting to DFMCR0-register is needed before use. Like an oscillator, this circuit requires time to stabilize. This is called the lock up time. The following example shows how DFM is used. DFMCR0 DFMCR1 EQU EQU LD LD LUP: BIT JR LD 00E8H 00E9H (DFMCR1), 00001011B (DFMCR0), 01X0XXXXB 5, (DFMCR0) NZ, LUP (DFMCR0), 10X0XXXXB ; ; ; ; DFM parameter setting. Set lock up time to 2 /4 MHz. Enables DFM operation and starts lock up. Detects end of lock up. Changes fc from 4 MHz to 16 MHz. (Changes fSYS from 2 MHz to 8 MHz.) 12 X: Don't care 01 10 Counts up by fOSCH During lock up After lock up Starts DFM operation. Starts lock up. Changes from 4 MHz to 16 MHz. Ends of lock up. Note: Input frequency limitation and correction for DFM Recommend to use Input frequency (High-speed oscillation) for DFM in the following condition. * * fOSCH = 4 to 9 MHz (Vcc = 3.0 to 3.6 V): Write 0BH to DFMCR1 fOSCH = 4 to 6.75 MHz (Vcc = 2.7 to 3.6 V): Write 0BH to DFMCR1 91C025-23 2007-02-28 TMP91C025 Limitation point on the use of DFM 1. It's prohibited to execute DFM enable/disable control in the SLOW mode (fs) (write to DFMCR0 LD LD (DFMCR0), C0H (DFMCR0), 00H ; ; Change the clock fDFM to fOSCH. DFM stop. 3. If you stop high-frequency oscillator during using DFM (DFMCR0 LD WUP: BIT JR LD LD LUP: BIT JR LD (SYSCR0), 11 - - - 1 - - B 2, (SYSCR0) NZ, WUP (SYSCR1), - - - - 0 - - - B (DFMCR0), 01 - 0 - - - - B 5, (DFMCR0) NZ, LUP (DFMCR0), 10 - 0 - - - - B ; ; ; ; ; ; ; ; High-frequency oscillator start up/warm-up start. Check for the flag of warm-up end. Change the system clock fs to fOSCH. DFM start up/lock up start. Check for the flag of lock up end. Change the system clock fOSCH to fDFM. (OK) Low-frequency oscillator operation mode (fs) (High-frequency oscillator operate) High-frequency oscillator operation mode (fOSCH) DFM start up DFM use mode (fDFM) LD LD LUP: BIT JR LD (SYSCR1), - - - - 0 - - - B (DFMCR0), 01 - 0 - - - - B 5, (DFMCR0) NZ, LUP (DFMCR0), 10 - 0 - - - - B ; ; ; ; ; Change the system clock fs to fOSCH. DFM start up/lock up start. Check for the flag of lock up end. Change the system clock fOSCH to fDFM. (Error) Low-frequency oscillator operation mode (fs) (High-frequency oscillator STOP) High-frequency oscillator start up DFM start up DFM use mode (fDFM) LD WUP: BIT JR LD LUP: BIT JR LD LD (SYSCR0), 11 - - - 1 - - B 2, (SYSCR0) NZ, WUP (DFMCR0), 01 - 0 - - - - B 5, (DFMCR0) NZ, LUP (DFMCR0), 10 - 0 - - - - B (SYSCR1), - - - - 0 - - - B ; ; ; ; ; ; ; ; High-frequency oscillator starts up/warm-up start. Check for the flag of warm-up end. DFM start up/lock up start. Check for the flag of lock up end. Change the internal clock fOSCH to fDFM. Change the system clock fs to fDFM. 91C025-24 2007-02-28 TMP91C025 (2) Change/stop control (OK) DFM use mode (fDFM) High-frequency oscillator operation mode (fOSCH) DFM stop Low-frequency oscillator operation mode (fs) High-frequency oscillator stop LD LD LD LD (DFMCR0), 11 - - - - - - B (DFMCR0), 00 - - - - - - B (SYSCR1), - - - - 1 - - - B (SYSCR0), 0 - - - - - - - B ; ; ; ; Change the system clock fDFM to fOSCH. DFM stop. Change the system clock fOSCH to fs. High-frequency oscillator stop. (Error) DFM use mode (fDFM) Low-frequency oscillator operation mode (fs) DFM stop High-frequency oscillator stop LD LD LD LD (SYSCR1), - - - - 1 - - - B (DFMCR0), 11 - - - - - - B (DFMCR0), 00 - - - - - - B (SYSCR0), 0 - - - - - - - B ; ; ; ; Change the system clock fDFM to fs. Change the internal clock (fc) fDFM to fOSCH. DFM stop. High-frequency oscillator stop. (OK) DFM use mode (fDFM) Set the STOP mode High-frequency oscillator operation mode (fOSCH) DFM stop HALT (High-frequency oscillator stop) LD (SYSCR2), - - - - 01 - - B ; Set the STOP mode. (This command can execute before use of DFM.) LD LD HALT (DFMCR0), 11 - - - - - - B (DFMCR0), 00 - - - - - - B ; ; ; Change the system clock fDFM to fOSCH. DFM stop. Shift to STOP mode. (Error) DFM use mode (fDFM) Set the STOP mode HALT (High-frequency oscillator stop) LD (SYSCR2), - - - - 01 - - B ; Set the STOP mode. (This command can execute before use of DFM.) HALT ; Shift to STOP mode. 91C025-25 2007-02-28 TMP91C025 3.3.6 Noise Reduction Circuits Noise reduction circuits are built in, allowing implementation of the following features. (1) Reduced drivability for high-frequency oscillator (2) Reduced drivability for low-frequency oscillator (3) Single drive for high-frequency oscillator (4) SFR protection of register contents (5) ROM protection of register contents The above functions are performed by making the appropriate settings in the EMCCR0 to EMCCR3 registers. (1) Reduced drivability for high-frequency oscillator (Purpose) Reduces noise and power for oscillator when a resonator is used. (Block diagram) fOSCH C1 Resonator EMCCR0 (Setting method) The drivability of the oscillator is reduced by writing 0 to EMCCR0 91C025-26 2007-02-28 TMP91C025 (2) Reduced drivability for low-frequency oscillator (Purpose) Reduces noise and power for oscillator when a resonator is used. (Block diagram) XT1 pin Enable oscillation EMCCR0 C1 Resonator C2 fS XT2 pin (Setting method) The drivability of the oscillator is reduced by writing 0 to EMCCR0 the (Purpose) Not need twin-drive and protect mistake operation by inputted noise to X2 pin when the external-oscillator is used. (Block diagram) fOSCH X1 pin Enable oscillation ( STOP + EMCCR0 < EXTIN > ) EMCCR0 X2 pin (Setting method) The oscillator is disabled and starts operation as buffer by writing 1 to EMCCR0 91C025-27 2007-02-28 TMP91C025 (4) Runaway provision with SFR protection register (Purpose) Provision in runaway of program by noise mixing. Write operation to specified SFR is prohibited so that provision program in runaway prevents that it is it in the state which is fetch impossibility by stopping of clock, memory control register (CS/WAIT controller, MMU) is changed. And error handling in runaway becomes easy by INTP0 interruption. Specified SFR list 1. CS/WAIT controller B0CS, B1CS, B2CS, B3CS, BEXCS, MSAR0, MSAR1, MSAR2, MSAR3, MAMR0, MAMR1, MAMR2, MAMR3 2. MMU LOCAL0/1/2/3 3. Clock gear SYSCR0, SYSCR1, SYSCR2, EMCCR0, EMCCR3 4. DFM DFMCR0, DFMCR1 (Operation explanation) Execute and release of protection (write operation to specified SFR) becomes possible by setting up a double key to EMCCR1 and EMCCR2 register. (Double key) 1st-KEY: Succession writes in 5AH at EMCCR1 and A5H at EMCCR2 2nd-KEY: Succession writes in A5H at EMCCR1 and 5AH at EMCCR2 A state of protection can be confirmed by reading EMCCR0 91C025-28 2007-02-28 TMP91C025 (5) Runaway provision with ROM protection register (Purpose) Provision in runaway of program by noise mixing. (Operation explanation) When write operation was executed for external three kinds of ROM by runaway of program, INTP1 is occurred and detects runaway function. Three kinds of ROM is fixed as for Flash ROM (Option program ROM), Data ROM, Program ROM are as follows on the logical address memory map. 1. Flash ROM: 2. Data ROM: 3. Program ROM: Address 400000H to 7FFFFFH Address 800000H to BFFFFFH Address C00000H to FFFFFFH For these address, admission/prohibition of detection of write operation sets it up with EMCCR3 91C025-29 2007-02-28 TMP91C025 3.3.7 Standby Controller (1) HALT modes When the HALT instruction is executed, the operating mode switches to IDLE2, IDLE1 or STOP mode, depending on the contents of the SYSCR2 TMRA01 TMRA23 SIO0 SIO1 AD converter WDT SFR TA01RUN b. IDLE1: Only the oscillator and the RTC (Real-time clock) and MLD continue to operate. c. STOP: All internal circuits stop operating. The operation of each of the different HALT modes is described in Table 3.3.3. Table 3.3.3 I/O Operation during HALT Modes HALT Mode SYSCR2 CPU I/O ports TMRA Block SIO AD converter WDT LCDC, Interrupt controller RTC, MLD Operate Possible to operate Available to select operation block Stop was executed. IDLE2 11 Stop Keep the state when the HALT instruction IDLE1 10 STOP 01 See Table 3.3.6, Table 3.3.7 91C025-30 2007-02-28 TMP91C025 (2) How to release the HALT mode These halt states can be released by resetting or requesting an interrupt. The halt release sources are determined by the combination between the states of interrupt mask register 91C025-31 2007-02-28 TMP91C025 Table 3.3.4 Source of Halt State Clearance and Halt Clearance Operation Status of Received Interrupt HALT Mode Source of halt state clearance INTWDT INT0 to INT3 (Note 1) INTALM0 to INTALM4 Interrupt INTTA0 to INTTA3 INTRX0 to INTRX1, TX0 to TX1 INTAD INTKEY INTRTC INTLCD RESET Interrupt Enabled Interrupt Disabled (Interrupt level) (Interrupt mask) (Interrupt level) < (Interrupt mask) IDLE2 IDLE1 STOP x x x x x x x x x x *1 *1 IDLE2 - IDLE1 STOP - - x x x x x x *1 x x x x x x Initialize LSI x x *1 x x : After clearing the HALT mode, CPU starts interrupt processing. : After clearing the HALT mode, CPU resumes executing starting from instruction following the HALT instruction. x: It can not be used to release the HALT mode. -: The priority level (Interrupt request level) of non-maskable interrupts is fixed to 7, the highest priority level. There is not this combination type. *1: Releasing the HALT mode is executed after passing the warm-up time. Note 1: When the HALT mode is cleared by an INT0 interrupt of the level mode in the interrupt enabled status, hold level H until starting interrupt processing. If level L is set before holding level L, interrupt processing is correctly started. (Example) Releasing IDLE1 mode An INT0 interrupt clears the halt state when the device is in IDLE1 mode. Address 8200H 8203H 8206H 8209H 820BH 820EH INT0 LD LD LD EI LD HALT (PBFC), 00H (IIMC), 00H (INTE0AD), 06H 5 (SYSCR2), 88H ; Sets PB3 to INT0. ; Selects INT0 interrupt rising edge. ; Sets INT0 interrupt level to 6. ; Sets interrupt level to 5 for CPU. ; Sets HALT mode to IDLE1 Mode. ; Halts CPU. INT0 interrupt routine RETI 820FH LD XX, XX 91C025-32 2007-02-28 TMP91C025 (3) Operation a. IDLE2 mode In IDLE2 mode only specific internal I/O operations, as designated by the IDLE2 setting register, can take place. Instruction execution by the CPU stops. Figure 3.3.6 illustrates an example of the timing for clearance of the IDLE2 mode halt state by an interrupt. X1 A0 to A23 D0 to D15 RD WR Data Data Interrupt for release IDLE2 mode Figure 3.3.6 Timing Chart for IDLE2 Mode Halt State Cleared by Interrupt b. IDLE1 mode In IDLE1 mode, only the internal oscillator and the RTC, MLD continue to operate. The system clock in the MCU stops. The pin status in the IDLE1 mode is depended on setting the register SYSCR2 X1 A0 to A23 D0 to D15 RD WR Data Data Interrupt for release IDLE1 mode Figure 3.3.7 Timing Chart for IDLE1 Mode Halt State Cleared by Interrupt 91C025-33 2007-02-28 TMP91C025 c. STOP mode When STOP mode is selected, all internal circuits stop, including the internal oscillator pin status in STOP mode depends on the settings in the SYSCR2 Warm-up time X1 A0 to A23 D0 to D15 RD WR Data Data Interrupt for release STOP mode Figure 3.3.8 Timing Chart for STOP Mode Halt State Cleared by Interrupt Table 3.3.5 Sample Warm-up Times after Clearance of STOP Mode at fOSCH = 36 MHz, fs =32.768 kHz SYSCR0 0 (fc) 1 (fs) SYSCR2 7.1 s 7.8 ms 8 10 (214) 0.455 ms 500 ms 11 (216) 1.820 ms 2000 ms 91C025-34 2007-02-28 TMP91C025 (Setting example) The STOP mode is entered when the low-frequency operates, and high-frequency operates after releasing due to INTx. Address SYSCR0 SYSCR1 SYSCR2 8FFDH 9000H 9002H 9005H INTx EQU EQU EQU LD LD LD HALT 00E0H 00E1H 00E2H (SYSCR1), 08H (SYSCR2), - X1001-1B (SYSCR0), 011000 - - B ; fSYS = fs/2. ; Sets warm-up time to 2 /fOSCH. ; Operates high-frequency after released. - : No change Clears and starts hit warm-up timer. (High-frequency) End INTx interrupt routine 14 9006H LD XX, XX RETI Note: When different modes are used before and after STOP mode as the above mentioned , there is possible to release the HALT mode without changing the operation mode by acceptance of the halt release interrupt request during execution of HALT instruction (during 6 states). In the system which accepts the interrupts during execution HALT instruction, set the same operation mode before and after the STOP mode. 91C025-35 2007-02-28 TMP91C025 Table 3.3.6 Input Buffer State Table Input Buffer State When the CPU is Input Port Name Function Name During Reset operating When Used as function Pin D0-7 P10-17 P56 (*1) P80-82 (*2) P83 (*2) P90 (*1) P91 (*1) P92 (*1) P93 (*1) P94 (*1) P95 (*1) P96 (*1) P97 (*1) PB3 PB4 PB5 PB6 PC0 PC3 (*1) PC1 PC2 PC4 PC5 (*1) PZ2-Z3 RESET , In HALT mode(IDLE2) When Used as function Pin OFF In HALT mode(IDLE1/STOP) Condition A (Note) When Used as function Pin When Used as Input Port - OFF OFF - OFF OFF ON - ON OFF Condition B (Note) When Used as function Pin - When Used as Input Port - When Used as Input Port - OFF When Used as Input Port - OFF D8-15 WAIT ON upon external read ON OFF ON - ON ON ON upon port read - ON OFF - ADTRG KI0 KI1 KI2 KI3 KI4 KI5 KI6 KI7 INT0, PS INT1, TA0IN INT2 INT3 - - RXD0 SCLK0, CTS0 ON RXD1 SCLK1, CTS1 - - - ON: The buffer is always turned on. A current flows *1: Port having a pull-up/pull-down resistor. the input buffer if the input pin is not driven. OFF: The buffer is always turned off. -: No applicable *2:AIN input does not cause a current to flow through the buffer. ON - - - OFF - - ON - - ON OFF - ON - - - OFF OFF ON - OFF ON OFF OFF ON ON ON ON ON ON ON ON ON ON AM0,AM1 X1,XT1 ON ON IDLE1 : ON , STOP : OFF Note: Condition A/B are as follows. SYSCR2 register setting 91C025-36 2007-02-28 TMP91C025 Table 3.3.7 Output Buffer State Table Output Buffer State When the CPU is Port Name Output Function Name operating During Reset When Used as function Pin D0-7 P10-17 A0-15 P20-27 P56 (*1) P60 P61 P62 P63 P64 P65 PA0 PA1 PA2 PA3 PB3-B4 PB5 PB6 PC0 PC1,C4 PC2 PC3 (*1) PC5 PD0 (*1) PD1 PD2 PD3 PD4 PD7 RD , WR In HALT mode(IDLE2) When Used as function Pin OFF In HALT mode(IDLE1/STOP) Condition A (Note) When Used as Output Port - OFF OFF OFF - - Condition B (Note) When Used as function Pin When Used as Output Port - ON - When Used as Output Port - ON - When Used When Used as Output Port - ON - as function Pin - OFF D8-15 - A16-23 - CS0 CS1 CS2 , CS2A CS3 ON upon external write ON OFF ON - ON - ON - EA24, CS2B , SRLB EA25, CS2C , SRUB KO0, ALARM , MLDALM ON ON ON ON ON OFF OFF ON ON KO1,TA1OUT KO2,TA3OUT KO3,SCOUT - PX PY TXD0 - SCLK0 TXD1 SCLK1 D1BSCP D2BLP D3BFR DLEBCD DOFFB MLDALM - HWR - - - - - ON OFF - - - ON OFF ON ON - - - - ON ON OFF ON ON ON ON OFF ON - OFF ON - - ON - - OFF IDLE1 : ON , STOP : Output "H" level IDLE1 : ON , STOP : High-Z - ON PZ2 (*1) PZ3 (*1) X2 XT2 R/W, SRWR - - ON ON ON ON : The buffer is always turned on. When the bus is *1:Port having a pull-up/pull-down resistor. released , however ,output buffers for some pins are turned off. OFF: The buffer is always turned off. - : No applicable Note: Condition A/B are as follows. SYSCR2 register setting 91C025-37 2007-02-28 TMP91C025 3.4 Interrupts Interrupts are controlled by the CPU interrupt mask register SR A (fixed) individual interrupt vector number is assigned to each interrupt. One of six (variable) priority level can be assigned to each maskable interrupt. The priority level of non-maskable interrupts are fixed at 7 as the highest level. When an interrupt is generated, the interrupt controller sends the piority of that interrupt to the CPU.If multiple interrupts are generated simultaneously, the interrupt controller sends the interrupt with the highest priority to the CPU. (The highest priority is level 7 using for non-maskable interrupts.) The CPU compares the priority level of the interrupt with the value of the CPU interrupt mask register 91C025-38 2007-02-28 TMP91C025 Interrupt processing Micro DMA soft start request Interrupt specified by micro DMA start vector? Yes No Clear interrupt request flag Interrupt vector value V read Interrupt request F/F clear Data transfer by micro DMA General-purpose interrupt processing PUSH PC PUSH SR SR Count Count1 Micro DMA processing Count = 0 No Yes Clear vector register generating micro DMA trasfer and interrupt (INTTC0 - 3) PC (FFFF00H + V) Interrupt processing program RETI instruction POP SR POP PC INTNESTINTNEST - 1 End Figure 3.4.1 Overall Interrupt Processing Flow 91C025-39 2007-02-28 TMP91C025 3.4.1 General-purpose Interrupt Processing When the CPU accepts an interrupt, it usually performs the following sequence of operations. That is also the same as TLCS-900/L and TLCS-900/H. (1) The CPU reads the interrupt vector from the interrupt controller. If the same level interrupts occur simultaneously, the interrupt controller generates an interrupt vector in accordance with the default priority and clears the interrupt request. (The default priority is already fixed for each interrupt: the smaller vector value has the higher priority level.) (2) The CPU pushes the value of program counter (PC) and status register (SR) onto the stack area (indicated by XSP). (3) The CPU sets the value which is the priority level of the accepted interrupt plus 1 (+1) to the interrupt mask register 91C025-40 2007-02-28 TMP91C025 Table 3.4.1 TMP91C025 Interrupt Vectors Table Default Priority 1 2 3 4 5 6 7 8 9 - 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Maskable NonMaskable Type Interrupt Source and Source of Micro DMA Request Reset or "SWI 0" instruction "SWI 1" instruction INTUNDEF: illegal instruction or "SWI 2" instruction "SWI 3" instruction "SWI 4" instruction "SWI 5" instruction "SWI 6" instruction "SWI 7" instruction INTWD: Watchdog timer Micro DMA (MDMA) INT0 pin INT1 pin INT2 pin INT3 pin INTALM0: ALM0 (8192 Hz) INTALM1: ALM1 (512 Hz) INTALM2: ALM2 (64 Hz) INTALM3: ALM3 (2 Hz) INTALM4: ALM4 (1 Hz) INTTA0: INTTA1: INTTA2: INTTA3: INTRX0: INTTX0: INTRX1: INTTX1: INTAD: INTKEY: INTRTC: INTLCD: INTP0: INTP1: INTTC0: INTTC1: INTTC2: INTTC3: (Reserved) to (Reserved) 8-bit timer0 8-bit timer1 8-bit timer2 8-bit timer3 Serial reception (Channel 0) Serial transmission (Channel 0) Serial reception (Channel 1) Serial transmission (Channel 1) AD conversion end Key wake up RTC (Alarm interrupt) LCDC/LP pin Protect 0 (WR to special SFR) Protect 1 (WR to ROM) Micro DMA end (Channel 0) Micro DMA end (Channel 1) Micro DMA end (Channel 2) Micro DMA end (Channel 3) Vector Micro Vector Reference DMA Start Value (V) Address Vector 0000H 0004H 0008H 000CH 0010H 0014H 0018H 001CH 0024H - 0028H 002CH 0030H 0034H 0038H 003CH 0040H 0044H 0048H 004CH 0050H 0054H 0058H 005CH 0060H 0064H 0068H 006CH 0070H 0074H 007CH 0080H 0084H 0088H 008CH 0090H 0094H 0098H to 00FCH FFFF00H FFFF04H FFFF08H FFFF0CH FFFF10H FFFF14H FFFF18H FFFF1CH FFFF24H - FFFF28H FFFF2CH FFFF30H FFFF34H FFFF38H FFFF3CH FFFF40H FFFF44H FFFF48H FFFF4CH FFFF50H FFFF54H FFFF58H FFFF5CH FFFF60H FFFF64H FFFF68H FFFF6CH FFFF70H FFFF74H FFFF7CH FFFF80H FFFF84H FFFF88H FFFF8CH FFFF90H FFFF94H FFFF98H to FFFFFCH - - - - - - - - - - 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1FH 20H 21H - - - - - to - 91C025-41 2007-02-28 TMP91C025 3.4.2 Micro DMA Processing In addition to general-purpose interrupt processing, the TMP91C025 supprots a micro DMA function. Interrupt requests set by micro DMA perform micro DMA processing at the highest priority level (level 6) among maskable interrupts, regardless of the priority level of the particular interrupt source. The micro DMA has 4 channels and is possible continuous transmission by specifing the say later burst mode. Because the micro DMA function has been implemented with the cooperative operation of CPU, when CPU goes to a standby mode by HALT instruction, the requirement of micro DMA will be ignored (Pending). (1) Micro DMA operation When an interrupt request specified by the micro DMA start vector register is generated, the micro DMA triggers a micro DMA request to the CPU at interrupt priority level 6 and starts processing the request in spite of any interrupt source's level. The micro DMA is ignored on Note: If the priority level of micro DMA is set higher than that of other interrupts, CPU operates as follows. In case INTxxx interrupt is generated first and then INTyyy interrupt is generated between checking "Interrupt specified by micro DMA start vector" (in the Figure 3.4.1) and reading interrupt vector with setting below. The vector shifts to that of INTyyy at the time. This is because the priority level of INTyyy is higher than that of INTxxx. In the interrupt routine, CPU reads the vector of INTyyy because cheking of micro DMA has finished. And INTyyy is generated regardless of transfer counter of micro DMA. INTxxx: level 1 without micro DMA INTyyy: level 6 with micro DMA 91C025-42 2007-02-28 TMP91C025 If a micro DMA request is set for more than one channel at the same time, the priority is not based on the interrupt priority level but on the channel number. The smaller channel number has the higher priority (Channel 0 (High) > channel 3 (Low)). While the register for setting the transfer source/transfer destination addresses is a 32-bit control register, this register can only effectively output 24-bit addresses. Accordingly, micro DMA can access 16 Mbytes (the upper eight bits of the 32 bits are not valid). Three micro DMA transfer modes are supported: 1-byte transfer, 2-byte (one word) transfer, and 4-byte transfer. After a transfer in any mode, the transfer source/destination addresses are increased, decreased, or remain unchanged. This simplifies the transfer of data from I/O to memory, from memory to I/O , and from I/O to I/O. For details of the transfer modes, see 3.4.2 (4) Transfer mode register. As the transfer counter is a 16-bit counter, micro DMA processing can be set for up to 65536 times per interrupt source. (The micro DMA processing count is maximized when the transfer counter initial value is set to 0000H.) Micro DMA processing can be started by the 24 interrupts shown in the micro DMA start vectors of Table 3.4.1 and by the micro DMA soft start, making a total of 25 interrupts. Figure 3.4.2 shows the word transfer micro DMA cycle in transfer destination address INC mode (except for counter mode, the same as for other modes). (The conditions for this cycle are based on an external 16-bit bus, 0 waits, trandfer source/transfer destination addresses both even-numberd values). 1 state Note 1 DM2 DM3 DM4 DM5 DM6 Note 2 DM7 DM8 DM1 X1 A0 to A23 RD WR / HWR Trasfer source address Trasger destination address D0 to D15 Input Output Figure 3.4.2 Timing for Micro DMA Cycle States 1 to 3: Instruction fetch cycle (Gets next address code). If 3 bytes and more instruction codes are inserted in the instruction queue buffer, this cycle becomes a dummy cycle. States 4 to 5: Micro DMA read cycle State 6: Dummy cycle (the address bus remains unchanged from state 5) States 7 to 8: Micro DMA write cycle Note 1: If the source address area is an 8-bit bus, it is increased by two states. If the source address area is a 16-bit bus and the address starts from an odd number, it is increased by two states. Note 2: If the destination address area is an 8-bit bus, it is increased by two states. If the destination address area is a 16-bit bus and the address starts from an odd number, it is increased by two states. 91C025-43 2007-02-28 TMP91C025 (2) Soft start function In addition to starting the micro DMA function by interrupts, TMP91C025 includes a micro DMA software start function that starts micro DMA on the generation of the write cycle to the DMAR register. Writing 1 to each bit of DMAR register causes micro DMA once (If write 0 to each bits, micro DMA doesn't operate). At the end of transfer, the corresponding bit of the DMAR register is automatically cleared to 0. Only one-channel can be set for micro DMA at once. (Do not write 1 to plural bits.) When writing again 1 to the DMAR register, check whether the bit is 0 before writing 1. If read 1, micro DMA transfer isn't started yet. When a burst is specified by DMAB register, data is continuously transferred until the value in the micro DMA transfer counter is 0 after start up of the micro DMA. If the value in the micro DMA transfer counter is 0 after start up of the micro DMA transfer counter doesn't change. Don't use Read-modify-write instruction to avoid writing to other bits by mistake. Symbol Name DMA DMAR request register Address 89H (Prohibit RMW) 7 6 5 4 3 DMAR3 0 2 DMAR2 0 R/W 1 DMAR1 0 0 DMAR0 0 DMA request (3) Transfer control registers The transfer source address and the transfer destination address are set in the following registers in CPU. Data setting for these registers is done by an LDC cr,r instruction. Channel 0 DMAS0 DMAD0 DMAC0 DMAM0 DMA source address register 0: DMA counter register 0: DMA mode register 0. only use LSB 24 bits. 1 to 65536 . DMA destination address register 0: only use LSB 24 bits. Channel 3 DMAS3 DMAD3 DMAC3 DMAM3 8 bits 16 bits 32 bits DMA source address register 3. DMA destination address register 3. DMA counter register 3. DMA mode register 3. 91C025-44 2007-02-28 TMP91C025 (4) Detailed description of the transfer mode register 8 bits DMAM0 to DMAM3 0 0 0 Mode Note: When setting a value in this register, write 0 to the upper 3 bits. Number of Transfer Bytes 000 (fixed) 000 00 01 10 001 00 01 10 010 00 01 10 011 00 01 10 100 00 01 10 101 00 Byte transfer Word transfer 4-bit transfer Counter mode Byte transfer Word transfer 4-bit transfer Byte transfer Word transfer 4-bit transfer Byte transfer Word transfer 4-bit transfer Byte transfer Word transfer 4-bit transfer Mode Description Transfer destination address INC mode ................................................ I/O to memory (DMADn+) (DMASn) DMACn DMACn - 1 If DMACn = 0, then INTTCn is generated. Transfer destination address DEC mode ................................................ I/O to memory (DMADn-) (DMASn) DMACn DMACn - 1 If DMACn = 0, then INTTCn is generated. Transfer source address INC mode ................................................ Memory to I/O (DMADn) (DMASn+) DMACn DMACn - 1 If DMACn = 0, then INTTCn is generated. Transfer source address DEC mode ................................................ Memory to I/O (DMADn) (DMASn-) DMACn DMACn - 1 If DMACn = 0, then INTTCn is generated. Fixed address mode ........................................................ I/O to I/O (DMADn) (DMASn-) DMACn DMACn - 1 If DMACn = 0, then INTTCn is generated. Minimum Number of Execution Time Execution States at fc = 36 MHz 8 states 444 ns 12 states 667 ns 8 states 444 ns 12 states 667 ns 8 states 444 ns 12 states 667 ns 8 states 444 ns 12 states 667 ns 8 states 444 ns 12 states 667 ns ..................... For counting number of times interrupt is generated DMASn DMASn + 1 DMACn DMACn - 1 If DMACn = 0, then INTTCn is generated. 5 states 278 ns Note 1: n is the corresponding micro DMA channels 0 to 3 DMADn+/DMASn+: Post-increment (increment register value after transfer) DMADn-/DMASn-: Post-decrement (decrement register value after transfer) The I/Os in the table mean fixed address and the memory means increment (INC) or decrement (DEC) addresses. Note 2: Execution time is under the condition of: 16-bit bus width (both translation and destination address area) /0 waits/ fc = 36 MHz/selected high frequency mode (fc x 1) Note 3: Do not use an undefined code for the transfer mode register except for the defined codes listed in the above table. 91C025-45 2007-02-28 TMP91C025 3.4.3 Interrupt Controller Operation The block diagram in Figure 3.4.3 shows the interrupt circuits. The left-hand side of the diagram shows the interrupt controller circuit. The right-hand side shows the CPU interrupt request signal circuit and the halt release circuit. For each of the 36 interrupt channels there is an interrupt request flag (consisting of a flip-flop), an interrupt priority setting register and a micro DMA start vector register. The interrupt request flag latches interrupt requests from the peripherals. The flag is cleared to 0 in the following cases: * * * * * When reset occurs When the CPU reads the channel vector after accepted its interrupt When executing an instruction that clears the interrupt (Write DMA start vector to INTCLR register) When the CPU receives a micro DMA request (When micro DMA is set) When the micro DMA burst transfer is terminated An interrupt priority can be set independently for each interrupt source by writing the priority to the interrupt priority setting register (e.g. INTE0AD or INTE12). 6 interrupt priorities levels (1 to 6) are provided. Setting an interrupt source's priority level to 0 (or 7) disables interrupt requests from that source. The priority of non-maskable interrupts (Watchdog timer interrupts) is fixed at 7. If interrupt request with the same level are generated at the same time, the default priority (The interrupt with the lowest priority or, in other words, the interrupt with the lowest vector value) is used to determine which interrupt request is accepted first. The 3rd and 7th bits of the interrupt priority setting register indicate the state of the interrupt request flag and thus whether an interrupt request for a given channel has occurred. The interrupt controller sends the interrupt request with the highest priority among the simulateous interrupts and its vector address to the CPU. The CPU compares the priority value 91C025-46 2007-02-28 Interrupt controller Interrupt request F/F S R V = 20H V = 24H CPU 1 Q Interrupt mask F/F RESET Interrupt Priority encoder request signal IFF2:0 3 3 INTRQ2 to 0 3 Interrupt level detect EI 1 to 7 DI 1 7 6 6 RESET Interrupt vector read Decoder A B C INTWD Priority setting register D Q CLR Interrupt request F/F Dn + 3 Interrupt request F/F 36 Interrupt vector generator Dn Dn + 1 Dn + 2 Y1 Y2 Y3 Y4 Y5 Y6 if INTRQ2 to 0 IFF 2 to 0 then 1. Interrupt request signal INT0 Reset SQ R D0 D1 Interrupt vector read Micro DMA acknowledge D2 D3 D4 D5 D6 D7 1 A 2 Highest priority B 3 interrupt 4 level select C 5 6 7 INT1 INT2 INT3 INTALM0 INTALM1 INTALM2 INTALM3 INTALM4 INTTA0 V = 28H V = 2CH V = 30H V = 34H V = 38H V = 3CH V = 40H V = 44H V = 48H V = 4CH During IDLE1 During STOP Figure 3.4.3 Block Diagram of Interrupt Controller 91C025-47 Interrupt vector read V = 84H V = 88H V = 8CH V = 90H V = 94H HALT release Micro DMA Counter 0 Interrupt RESET INT0, 1, 2, 3, INTKEY, INTRTC, INTALM 4 input OR 4 if IFF = 7 then 0 0 1 2 3 Micro DMA channel priority encoder A B 2 2 Micro DMA request INTP1 INTTC0 INTTC1 INTTC2 INTTC3 Micro DMA start vector setting register Soft start 34 S Selector D5 D4 D3 D2 D1 D0 DQ INTTC0 6 RESET DMA0V DMA1V DMA2V DMA3V Micro DMA channel specification TMP91C025 2007-02-28 TMP91C025 (1) Interrupt level setting registers Symbol Name Address INT0 and INTE0AD 7 IADC R 0 6 INTAD IADM2 0 INT2 I2M2 0 INTALM4 IA4M2 0 INTALM1 IA1M2 0 INTALM3 IA3M2 0 ITA1M2 0 ITA3M2 0 INTKEY IKM2 0 5 IADM1 R/W 0 I2M1 R/W 0 IA4M1 R/W 0 IA1M1 R/W 0 IA3M1 R/W 0 ITA1M1 R/W 0 ITA3M1 R/W 0 IKM1 R/W 0 4 IADM0 0 I2M0 0 IA4M0 0 IA1M0 0 IA3M0 0 ITA1M0 0 ITA3M0 0 IKM0 0 3 I0C R 0 I1C R 0 I3C R 0 IA0C R 0 IA2C R 0 ITA0C R 0 ITA2C R 0 IRC R 0 2 INT0 I0M2 0 INT1 I1M2 0 INT3 I3M2 0 INTALM0 IA0M2 0 INTALM2 IA2M2 0 ITA0M2 0 ITA2M2 0 INTRTC IRM2 0 1 I0M1 R/W 0 I1M1 R/W 0 I3M1 R/W 0 IA0M1 R/W 0 IA2M1 R/W 0 ITA0M1 R/W 0 ITA2M1 R/W 0 IRM1 R/W 0 0 I0M0 0 I1M0 0 I3M0 0 IA0M0 0 IA2M0 0 ITA0M0 0 ITA2M0 0 IRM0 0 INTAD enable 90H INT1 and INTE12 INT2 enable 91H I2C R 0 INT3 and INTE3ALM4 INTALM4 enable INTALM0 92H IA4C R 0 INTEALM01 and INTALM1 enable INTALM2 93H IA1C R 0 IA3C R 0 ITA1C R 0 ITA3C R 0 IKC R 0 INTEALM23 and INTALM3 enable INTTA0 94H INTTA1 (TMRA1) 95H INTTA0 (TMRA0) INTETA01 and INTTA1 enable INTTA2 INTTA3 (TMRA3) 96H INTTA2 (TMRA2) INTETA23 and INTTA3 enable INTRTC INTERTCKEY and INTKEY enable 97H Interrupt request flag lxxM2 0 0 0 0 1 1 1 1 lxxM1 0 0 1 1 0 0 1 1 lxxM0 0 1 0 1 0 1 0 1 Function (Write) Disables interrupt requests Sets interrupt priority level to 1 Sets interrupt priority level to 2 Sets interrupt priority level to 3 Sets interrupt priority level to 4 Sets interrupt priority level to 5 Sets interrupt priority level to 6 Disables interrupt requests 91C025-48 2007-02-28 TMP91C025 Symbol Name Interrupt INTES0 enable serial 0 Address 7 ITX0C R 0 6 INTTX0 ITX0M2 0 INTTX1 ITX1M2 0 INTLCD ILCDM2 0 INTTC1 ITC1M2 0 INTTC3 ITC3M2 0 INTP1 IP1M2 0 5 ITX0M1 0 ITX1M1 R/W 0 ILCDM1 R/W 0 ITC1M1 R/W 0 ITC3M1 R/W 0 IP1M1 R/W 0 4 ITX0M0 R 0 ITX1M0 0 ILCDM0 0 ITC1M0 0 ITC3M0 0 IP1M0 0 3 IRX0C R/W 0 IRX1C R 0 - - - ITC0C R 0 ITC2C R 0 IP0C R 0 2 INTRX0 IRX0M2 0 INTRX1 IRX1M2 0 - - - INTTC0 ITC0M2 0 INTTC2 ITC2M2 0 INTP0 IP0M2 0 1 IRX0M1 0 IRX1M1 R/W 0 - - - ITC0M1 R/W 0 ITC2M1 R/W 0 IP0M1 R/W 0 0 IRX0M0 0 IRX1M0 0 - - ITC0M0 0 ITC2M0 0 IP0M0 0 98H R/W INTRX1 & INTES1 INTTX1 enable 99H ITXT1C R 0 INTELCD INTLCD enable 9AH ILCD1C R 0 INTTC0 & INTETC01 INTTC1 enable 9BH ITC1C R 0 INTTC2 & INTETC23 INTTC3 enable 9CH ITC3C R 0 INTP0 & INTEP01 INTP1 enable 9DH IP1C R 0 Interrupt request flag lxxM2 0 0 0 0 1 1 1 1 lxxM1 0 0 1 1 0 0 1 1 lxxM0 0 1 0 1 0 1 0 1 Function (Write) Disables interrupt requests Sets interrupt priority level to 1 Sets interrupt priority level to 2 Sets interrupt priority level to 3 Sets interrupt priority level to 4 Sets interrupt priority level to 5 Sets interrupt priority level to 6 Disables interrupt requests 91C025-49 2007-02-28 TMP91C025 (2) External interrupt control Symbol Name Address Interrupt IIMC input mode control (Prohibit RMW) 8CH 0 Always write 0. 0 Always write 0. 0 0: Rising 1: Falling 0 0: Rising 1: Falling 7 - 6 - 5 I3EDGE 4 I2EDGE W 3 I1EDGE 0 0: Rising 1: Falling 2 I0EDGE 0 0: Rising 1: Falling 1 I0LE 0 0: Edge 1: Level 0 - 0 write 0. INT3EDGE INT2EDGE INT1EDGE INT0EDGE INT0 mode Always INT0 level enable 0 1 edge detect INT High level INT (3) Interrupt request flag clear register The interrupt request flag is cleared by writing the appropriate micro DMA start vector, to the register INTCLR. For example, to clear the interrupt flag INT0, perform the following register operation after execution of the DI instruction. INTCLR 0AH: Clears interrupt request flag INT0. Symbol Name Address Interrupt INTCLR clear control 88H (Prohibit RMW) 0 0 0 7 6 5 CLRV5 4 CLRV4 3 CLRV3 W 2 CLRV2 0 1 CLRV1 0 0 CLRV0 0 Interrupt Vector (4) Micro DMA start vector registers This register assigns micro DMA processing to which interrupt source. The interrupt source with a micro DMA start vector that matches the vector set in this register is assigned as the micro DMA start source. When the micro DMA transfer counter value reaches zero, the micro DMA transfer end interrupt corresponding to the channel is sent to the interrupt controller, the micro DMA start vector register is cleared, and the micro DMA start source for the channel is cleared. Therefore, to continue micro DMA processing, set the micro DMA start vector register again during the processing of the micro DMA transfer end interrupt. If the same vector is set in the micro DMA start vector registers of more than one channel, the channel with the lowest number has a higher priority. Accordingly, if the same vector is set in the micro DMA start vector registers of two channels, the interrupt generated in the channel with the lower number is executed until micro DMA transfer is complete. If the micro DMA start vector for this channel is not set again, the next micro DMA is started for the channel with the higher number. (Micro DMA chaining.) 91C025-50 2007-02-28 TMP91C025 Symbol Name DMA0 Address 7 6 5 DMA0V5 4 DMA0V4 0 DMA1V4 0 DMA2V4 0 DMA3V4 0 3 DMA0V3 0 DMA1V3 0 DMA2V3 0 DMA3V3 0 R/W 2 DMA0V2 0 DMA1V2 0 DMA2V2 0 DMA3V2 0 1 DMA0V1 0 DMA1V1 0 DMA2V1 0 DMA3V1 0 0 DMA0V0 0 DMA1V0 0 DMA2V0 0 DMA3V0 0 DMA0V start vector 80H 0 DMA1V5 DMA0 start vector DMA1 DMA1V start vector 81H R/W 0 DMA2V5 82H 0 DMA3V5 83H 0 DMA1 start vector DMA2 DMA2V start vector R/W DMA2 start vector DMA3 DMA3V start vector R/W DMA3 start vector (5) Micro DMA burst specification Specifying the micro DMA burst continues the micro DMA transfer until the transfer counter register reaches zero after micro DMA start. Setting a bit which corresponds to the micro DMA channel of the DMAB registers mentioned below to 1 specifies a burst. Symbol Name DMA DMAR software request register DMA DMAB burst register 8AH Address 89H (Prohibit RMW) 7 6 5 4 3 DMAR3 R/W 0 DMAB3 0 2 DMAR2 R/W 0 DMAB2 R/W 0 1 DMAR1 R/W 0 DMAB1 0 0 DMAR0 R/W 0 DMAB0 0 1: DMA software request 1: DMA burst request 91C025-51 2007-02-28 TMP91C025 (6) Attention point The instruction execution unit and the bus interface unit of this CPU operate independently. Therefore, immediately before an interrupt is generated, if the CPU fetches an instruction that clears the corresponding interrupt request flag, the CPU may execute the instruction that clears the interrupt request flag (Note) between accepting and reading the interrupt vector. In this case, the CPU reads the default vector 0008H and reads the interrupt vector address FFFF08H. To avoid the avobe plogram, place instructions that clear interrupt request flags after a DI instruction. And in the case of setting an interrupt enable again by EI instruction after the execution of clearing instruction, execute EI instruction after clearing and more than 1-instructions (ex. "NOP" x 1 times) In the case of changing the value of the interrupt mask register INT0 level mode In level mode INT0 is not an edge-triggered interrupt. Hence, in level mode the interrupt request flip-flop for INT0 does not function. The peripheral interrupt request passes through the S input of the flip-flop and becomes the Q output. If the interrupt input mode is changed from edge mode to level mode, the interrupt request flag is cleared automatically. If the CPU enters the interrupt response sequence as a result of INT0 going from 0 to 1, INT0 must then be held at 1 until the interrupt response sequence has been completed. If INT0 is set to level mode so as to release a halt state, INT0 must be held at 1 from the time INT0 changes from 0 to 1 until the halt state is released. (Hence, it is necessary to ensure that input noise is not interpreted as a 0, causing INT0 to revert to 0 before the halt state has been released.) When the mode changes from level mode to edge mode, interrupt request flags which were set in level mode will not be cleared. Interrupt request flags must be cleared using the following sequence. DI LD (IIMC), 00H ; Switches interrupt input mode from level mode to edge mode. LD (INTCLR), 0AH ; Clears interrupt request flag. NOP EI INTRX The interrupt request flip-flop can only be cleared by a reset or by reading the serial channel receive buffer. It cannot be cleared by writing INTCLR register. ; Wait EI instruction Note: The following instructions or pin input state changes are equivalent to instructions that clear the interrupt request flag. Instructions which switch to level mode after an interrupt request has been generated in edge mode. The pin input change from high to low after interrupt request has been generated in level mode. (H L) INTRX: Instruction which read the receive buffer. INT0: 91C025-52 2007-02-28 TMP91C025 3.5 Port Functions The TMP91C025 features 38-bit settings which relate to the various I/O ports. As well as general-purpose I/O port functionality, the port pins also have I/O functions which relate to the built-in CPU and internal I/Os. Table 3.5.1 lists the functions of each port pin. Table 3.5.2, Table 3.5.4 lists I/O registers and their specifications. Table 3.5.1 Port Functions (R: PU = with programmable pull-up resistor/U = with pull-up resistor) Port Name Port 1 Port 2 Port 5 Port 6 Pin Name P10 to P17 P20 to P27 P56 P60 P61 P62 P63 P64 P65 Number of Pins 8 8 1 1 1 1 1 1 1 1 1 1 1 8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Direction I/O Output I/O Output Output Output Output Output Output Input Input Input Input Input Output Output Output Output I/O I/O Input Input I/O I/O I/O I/O I/O I/O Output Output Output Output Output Output I/O I/O R - - PU - - - - - - - - - - U - - - - - - - - - - PU - - PU - - - - - - PU PU Direction Setting Unit Bit (Fixed) Bit (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) Bit Bit (Fixed) (Fixed) Bit Bit Bit Bit Bit Bit (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) Bit Bit Pin Name for Built-in Function D8 to D15 A16 to A23 WAIT CS0 CS1 CS2 , CS2A CS3 EA24, CS2B , SRLB EA25, CS2C , SRUB AN0 AN1 AN2, MX AN3, ADTRG , MY KI0 to KI7 KO0, ALARM , MLDALM KO1, TA1OUT KO2, TA3OUT KO3, SCOUT INT0, PS INT1, TA0IN INT2, PX INT3, PY TXD0 RXD0 SCLK0, CTS0 TXD1 RXD1 SCLK1, CTS1 D1BSCP D2BLP D3BFR DLEBCD DOFFB MLDALM HWR Port 8 P80 P81 P82 P83 Port 9 Port A P90 to P97 PA0 PA1 PA2 PA3 PB3 PB4 PB5 PB6 Port B Port C PC0 PC1 PC2 PC3 PC4 PC5 Port D PD0 PD1 PD2 PD3 PD4 PD7 Port Z PZ2 PZ3 R/ W , SRWR 91C025-53 2007-02-28 TMP91C025 Table 3.5.2 I/O Registers and Specifications (1/2) Port Port 1 (Note 1) Port 2 Port 5 Port 6 P20 to P27 P56 P60 to P65 P60 P61 P62 X: Don't care I/O Register PnCR 0 1 X None 0 0 0 1 1 1 X None 1 0 1 1 0 1 1 None None None 0 1 0 0 1 None 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 X 1 X 1 None 1 None None 0 0 0 1 1 1 1 1 0 1 None 1 1 0 1 1 0 0 None 0 1 None None None Pin Name P10 to P17 Input port Output port Specification Pn X X X X X 0 1 X X X X X X X X X X X X X PnFC PnFC2 D8 to D15 bus Output port A16 to A23 output WAIT input (Without PU) WAIT input (With PU) Output port CS0 output CS1 output CS2 output CS2A output P63 P64 CS3 output SRLB output CS2B output P65 EA24 output SRUB output CS2C output EA25 output Port 8 P80 to P83 P83 Port 9 Port A P90 to P97 PA0 to PA3 Input port AN0 to 3 input ADTRG input Input port KI0 to 7 input Output port KO0 to 3 output (CMOS) KO0 to 3 output (Open drain) PA0 PA1 PA2 PA3 Port B PB3 to PB4 PB3 PB4 PB5 PB6 ALARM output (Note 2) (Note 3) X X X X X X X 1 0 X X X X X X X X X X X X X MLDALM output TA1OUT output TA3OUT output SCOUT output Input port Output port INT0 input PS input INT1 input TA0IN input INT2 input PX output INT3 input PY output 91C025-54 2007-02-28 TMP91C025 Table 3.5.3 I/O Registers and Specifications (2/2) Port Port C X: Don't care I/O Register PnCR 0 1 1 0 0 1 0 1 0 0 1 0 Pin Name PC0 to PC5 PC0 PC1 PC2 Input port Output port TXD0 output RXD0 input SCLK0 input Specification Pn X X PnFC PnFC2 0 0 1 None 0 1 0 1 None 0 1 0 0 1 1 None (Note 4) (Note 4) (Note 4) (Note 4) (Note 4) (Note 4) (Note 4) (Note 4) (Note 4) (Note 4) 1 1 1 1 1 1 1 1 1 1 X X X X X X X X X X X X SCLK0 output CTS0 input PC3 PC4 PC5 TXD1 output RXD1 input SCLK1 input SCLK1 output CTS1 input Port D PD0 to PD7 PD0 PD1 PD2 PD3 PD4 PD7 Output port D1BSCP output D2BLP output D3BFR output DLEBCD output DOFFB output MLDALM output Input port Output port HWR output None 1 1 1 1 Port Z PZ2 to PZ3 PZ2 PZ3 0 1 1 0 1 0 0 1 1 1 R/ W output SRWR output Note 1: Port1 is only use for port or DATA bus (D8 to D15) by setting AM1 and AM0 pins. Note 2: In case using P80 to P83 for analog input ports of AD converter, set to ADMOD1 91C025-55 2007-02-28 TMP91C025 3.5.1 Port 1 (P10 to P17) Port 1 is an 8-bit general-purpose I/O port. Each bit can be set individually for input or output using the control register P1CR. Resetting , the control register P1CR to 0 and sets port 1 to input mode. In addition to functioning as a general-purpose I/O port, port 1 can also function as an address data bus (D8 to 15). Table 3.5.4 Function Setting of AM0/AM1 AM1 0 0 1 1 AM0 0 1 0 1 Function Setting after Reset Input port Data bus (D8 to D15) Don't use this setting Don't use this setting Reset Direction control (on bit basis) P1CR write Output Latch Internal data bus Output buffer P1 write Port 1 P10 to P17 (D8 to D15) P1 Read Figure 3.5.1 Port 1 91C025-56 2007-02-28 TMP91C025 3.5.2 Port 2 (P20 to P27) Port 2 is an 8-bit output port. In addition to functioning as a output port, port 2 can also function as an address bus (A16 to A23). Each bit can be set individually for address bus using the function register P2FC. Resetting sets all bits of the function register P2FC to 1 and sets port 2 to address bus. Reset S Function control Internal data bus (on bits basis) P2FC write S Output latch B P2 write A selector Port 2 P20 to P27 (A16 to A23) Output buffer P2 read Internal A16 to A23 Figure 3.5.2 Port 2 91C025-57 2007-02-28 TMP91C025 Port 1 Register 7 P1 P0 (0001H) (0000H) Bit symbol Read/Write After reset P17 6 P16 5 P15 4 P14 R/W 3 P13 2 P12 1 P11 0 P10 Data from external port (Output latch register is cleared to 0.) Port 1 Control Register 7 P1CR (0004H) Bit symbol Read/Write After reset (Note2) Function 0/1 0/1 0/1 0/1 P17C 6 P16C 5 P15C 4 P14C W 3 P13C 2 P12C 1 P11C 0 P10C 0/1 0/1 0/1 0/1 0: Input 1: Output Port 1 I/O setting 0: Input 1: Output Port 2 Register 7 P2 (0006H) Bit symbol Read/Write After reset 1 1 1 1 P27 6 P26 5 P25 4 P24 R/W 3 P23 1 2 P22 1 1 P21 1 0 P20 1 Port 2 Function Register 7 P2FC (0009H) Bit symbol Read/Write After reset Function 1 1 1 1 P27F 6 P26F 5 P25F 4 P24F W 3 P23F 1 2 P22F 1 1 P21F 1 0 P20F 1 0: Port 1: Address bus (A23 to A16) Note1: Read-modify-write is prohibited for P1CR and P2FC. Note2: It is set to "Port" or "Data bus" by AM pins state. Figure 3.5.3 Registers for Ports 1 and 2 91C025-58 2007-02-28 TMP91C025 3.5.3 Port Z (PZ2 to PZ3) Port Z is an 2-bit general-purpose I/O port. I/O is set using control register PZCR and PZFC. Resetting sets all bits of the output latch PZ to 1. In addition to functioning as a general-purpose I/O port, port Z also functions as I/O for the CPU's control/status signal. Resetting initializes PZ2 and PZ3 pins to input mode with pull-up register. Reset Direction control (on bit basis) PZCR write Function conrtol Internal data bus (on bit basis) PZFC write S Selector S Output latch PZ write HWR P-ch (Programmable pull up) A B PZ2 ( HWR ) Output buffer PZ read Figure 3.5.4 Port Z2 91C025-59 2007-02-28 TMP91C025 Reset Direction control (on bit basis) PZCR write Function conrtol (on bit basis) Internal data bus PZFC write S Selector S Output latch PZ write A B C R/W SRWR P-ch (Programmable pull up) PZ3 (R/ W , SRWR ) Output buffer PZ read Figure 3.5.5 Port Z3 91C025-60 2007-02-28 TMP91C025 Port Z register 7 PZ (007DH) Bit symbol Read/Write After reset Function 6 5 4 3 PZ3 R/W 2 PZ2 1 0 Data from external port (Note 1) 0(Output latch register) : Pull-up resistor OFF 1(Output latch register) : Pull-up resistor ON Port Z control register 7 PZCR (007EH) Bit symbol Read/Write After reset Function 0 6 5 4 3 PZ3C W 2 PZ2C 0 1 0 0: Input 1: Output Port Z function register 7 PZFC (007FH) Bit symbol Read/Write After reset Function 0 0: Port 1: R/ W , SRWR 6 5 4 3 PZ3F W 2 PZ2F 0 1 0 0: Port 1: HWR Note 1: Note 2: Note 3: Output latch register is set to 1. Read-modify-write is prohibited for registers PZCR and PZFC. When port Z is used in Input mode, the PZ register controls the built-in pull-up resistor. Read-modify-write is prohibited in input mode or I/O mode. Setting the built-in pull-up resistor may be depended on the states of the input pin. R/W, SRWR setting 0 1 Output SRWR 0 1 Input R/W Figure 3.5.6 Registers for Port Z 91C025-61 2007-02-28 TMP91C025 3.5.4 Port 5 (P56) Port 5 is an 1-bit general-purpose I/O port. I/O is set using control register P5CR and P5FC. Resetting sets all bits of the output latch P5 to 1. In addition to functioning as a general-purpose I/O port, port 5 also functions as I/O for the CPU's control/status signal. Resetting initializes P56 pins to input mode with pull-up resistor. Reset Direction control (on bit basis) P5CR write Internal data bus P-ch (Programmable pull up) S Output Latch P5 write P56 ( WAIT ) Output buffer Internal WAIT P5 read Figure 3.5.7 Port 5 (P56) 91C025-62 2007-02-28 TMP91C025 Port 5 register 7 P5 (000DH) Bit symbol Read/Write After reset 6 P56 R/W Data from external port (Output latch register is set to 1.) 0(Output latch register) : Pull-up resistor OFF 1(Output latch register) : Pull-up resistor ON 5 4 3 2 1 0 Function Port 5 control register 7 P5CR (0010H) Bit symbol Read/Write After reset Function 6 P56C W 0 0: Input 1: Output 5 4 3 2 1 0 Note1: Read-modify-write is prohibited for registers P5CR. Note2: When the P56/WAIT pin is to be use as the WAIT pin, P5CR Figure 3.5.8 Registers for Port 5 91C025-63 2007-02-28 TMP91C025 3.5.5 Port 6 (P60 to P65) Port 60 to 65 are 6-bit output ports. Resetting sets output latch of P62 to "0" and output latches of P60 to P61, P63 to P65 to 1. Port6 also function as chip-select output ( CS0 to CS3 ), extend address output (EA24, EA25) and extend chip-select output ( CS2A , CS2B and CS2C ). Writing 1 in the corresponding bit of P6FC, P6FC2 enables the respective functions. Resetting resets the P6FC, P6FC2 to 0, and sets all bits to output ports. Reset Function control 2 (on bit basis) P6FC2 write Funtion control (on bit basis) P6FC write S Output lacth P6 write A B C Selector D 1,1,1,1, SRLB SRUB 1,1, CS2A ,1, CS2B , CS2C CS0 , CS1 , CS2 , CS3 , EA24, EA25 Internal data bus P60 ( CS0 ), P61 ( CS1 ), P62 ( CS2 , CS2A ), P63 ( CS3 ), P64 (EA24, CS2B , SRLB ), P65 (EA25, CS2C , SRUB ) P6 read Figure 3.5.9 Port 6 91C025-64 2007-02-28 TMP91C025 Port 6 Register 7 P6 (0012H) Bit symbol Read/Write After reset 1 1 1 6 5 P65 4 P64 3 P63 R/W 2 P62 0 1 P61 1 0 P60 1 Port 6 Function Register 7 P6FC (0015H) Bit symbol Read/Write After reset Function 0 0: Port 1: EA25 0 0: Port 1: EA24 0 0: Port 1: CS3 6 5 P65F 4 P64F 3 P63F W 2 P62F 0 0: Port 1: CS2 1 P61F 0 0: Port 1: CS1 0 P60F 0 0: Port 1: CS0 Port 6 Function Register 2 7 P6FC2 (001BH) Bit symbol Read/Write After reset Function 0 6 5 P65F2 W 4 P64F2 0 3 - 2 P62F2 W 0 0: 1 - 0 - W 0 W 0 W 0 0: Always write 0. SRUB , CS2C , EA25 setting SRLB , CS2B , EA24 setting 0 1 0 0 1 P64 SRLB 1 EA24 CS2B 0 1 P65 SRUB EA25 CS2C Note: Read-modify-write is prohibited for P6FC and P6FC2. Figure 3.5.10 Registers for Port 6 91C025-65 2007-02-28 TMP91C025 3.5.6 Port 8 (P80 to P83) Port 8 is a 4-bit input port and can also be used as the analog input pins for the internal AD converter. P83 can also be used as ADTRG pin for the AD converter. P82, P83 can also be used as MX, MY pin for touch screen interface. Internal data bus Port 8 read Port 8 P80 to P83 (AN0 to AN3) Conversion result register AD Read AD converter Channel selector ADTRG (for P83 only) TSICR0 TSICR0 Figure 3.5.11 Port 8 Port 8 Register 7 P8 (0018H) Bit symbol Read/Write After reset Note: 6 5 4 3 P83 2 P82 R 1 P81 0 P80 Data from external port. The input channel selection of AD Converter, the permission of ADTRG input are set by AD Converter mode register ADMOD1. The input channel selection of AD Converter, the permission of MX, MY input are set by touch screen control register TSICR. Figure 3.5.12 Registers for Port 8 91C025-66 2007-02-28 TMP91C025 3.5.7 Port 9 (P90 to P97) Port 90 to 97 are 8-bit input ports with pull-up resistors. In addition to functioning as general-purpose I/O port, port 90 to 97 can also Key-on wakeup function as Key board interface. The various functions can each be enabled by writing 1 to the corresponding bit of the port 9 function register (P9FC). Resetting resets all bits of the register P9FC to 0 and sets all pins to be input port. INTKEY Rising edge detection P90 to P97 8-OR Internal data bus Reset Key-on enable (on bit basis) P9FC write P9 read P90 to P97 (KI0 to KI7) Pull-up resistor Figure 3.5.13 Port 9 When P9FC = 1, if either of input of KI0 to KI7 pins falls down, INTKEY interrupt is generated. INTKEY interrupt can be used to release all HALT mode. Port 9 register 7 P9 (0019H) Bit symbol Read/Write After reset P97 6 P96 5 P95 4 P94 R 3 P93 2 P92 1 P91 0 P90 Data from external port. Port 9 function register 7 P9FC (001DH) Bit symbol Read/Write After reset Function 0 0 0 0 0: Key-in disable P97F 6 P96F 5 P95F 4 P94F W 3 P93F 0 2 P92F 0 1 P91F 0 0 P90F 0 1: Key-in enable Key-in of Port 9 Disable Enable Note: Read-modify-write is prohibited for the registers P9FC. 0 1 Figure 3.5.14 Registers for Port 9 91C025-67 2007-02-28 TMP91C025 3.5.8 Port A (PA0 to PA3) Port A0 to PA3 are 4-bit output ports, and also used Key board interface pin KO0 to KO3 which can set open drain output buffer. Writing 1 to the corresponding bit of the port A function register (PAFC) enable the open drain output. In addition to functioning as output port, port A also function as output pin for internal clock (SCOUT), output pin for RTC alarm ( ALARM ) and output pin for melody/alarm generator (MLDALM, MLDALM ). Above setting is used the function register PAFC2 Resetting reset bits of the registers PA to 1 and PAFC, PAFC2 to 0, and all pin outputs 1. Reset Function control PAFC2 write Internal data bus Output buffer set PAFC write S S Output latch PA write A Y Selector B PA0 (KO0, ALARM , MLDALM ) Programmable open drain PA read MLDALM AS Y Selector B ALARM Figure 3.5.15 Port A0 91C025-68 2007-02-28 TMP91C025 Reset Function control PAFC2 write Internal data bus Output buffer set PAFC write S S Output latch PA write A Y Selector B Programmable open drain PA1 (KO1, TA1OUT) PA2 (KO2, TA3OUT) PA read TA1OUT TA3OUT Figure 3.5.16 Port A1, 2 Reset Function control PAFC2 write Internal data bus Output buffer set PAFC write S S Output latch PA write PA read A Y Selector B Programmable open drain PA3 (KO3, SCOUT) fFPH clock Figure 3.5.17 Port A3 91C025-69 2007-02-28 TMP91C025 Port A register 7 PA (001EH) Bit symbol Read/Write After reset 1 1 6 5 4 3 PA3 2 PA2 R/W 1 PA1 1 0 PA0 1 Port A function register 7 PAFC (0021H) Bit symbol Read/Write After reset Function 0 0 6 5 4 3 PA3F 2 PA2F W 1 PA1F 0 0 PA0F 0 0: CMOS output 1: Open drain 7 PAFC2 (0020H) Bit symbol Read/Write After reset Function 6 5 4 3 PA3F2 0 0: Port 1: SCOUT 2 PA2F2 W 0 0: Port 1: TA3OUT 1 PA1F2 0 0: Port 1: TA1OUT 0 PA0F2 0 0: Port 1: ALARM at Note: Read-modify-write is prohibited for PAFC and PAFC2. Figure 3.5.18 Registers for Port A 91C025-70 2007-02-28 TMP91C025 3.5.9 Port B (PB3 to PB6) Port B3 to PB6 is a 4-bit general-purpose I/O port. Each bit can be set individually for input or output. Resetting sets port B to be an input port. In addition to functioning as a general-purpose I/O port, port B3 to B6 has each external interruption input facility of INT0 to INT3. Edge selection of external interruption is establishes by IIMC register in the interrupt controller. And also, port B3 has PS input terminal, and port B4 has clock input terminal TA0IN of 8 bits timer 0, and port B5, B6 each has touch screen block listing PX, PY terminal. Timer output function and external interrupt function can be enabled by writing 1 to the corresponding bits in the port B function register (PBFC). Resetting resets all bits of the registers PBCR and PBFC to 0, and sets all bits to be input ports. (1) PB3 (INT0) Reset Direction control (on bits basis) PBCR write Internal data bus Function control (on bits basis) PBFC write S Output latch PB write SB Selector PB read A Level/edge select and Rising/falling select IIMC INT0 PS SYSCR2 Figure 3.5.19 Port B3 Note: After reset, input 1 to PB3 (INT0, PS ) -pin, because it is worked as PS input pin. 91C025-71 2007-02-28 TMP91C025 (2) PB4 (INT1) Reset Direction control (on bits basis) PBCR write Internal data bus Function control (on bits basis) PBFC write S Output latch PB write SB Selector PB read A PB4 (INT1, TA0IN) INT1 Rising/falling edge detection IIMC TA0IN Figure 3.5.20 Port B4 91C025-72 2007-02-28 TMP91C025 (3) PB5 (INT2), PB6(INT3) Reset Function control (on bits basis) Internal data bus AVCC TSICR0 PBFC write PB read TSICR1 Only for PB5 S A Debounce circuit . INT2 INT3 Rising/falling edge detection IIMC Selector B TSICR0 Figure 3.5.21 Port B5, B6 91C025-73 2007-02-28 TMP91C025 Port B Register 7 PB (0022H) Bit symbol Read/Write After reset 6 PB6 5 PB5 R/W 4 PB4 3 PB3 2 1 0 Data from external port (Note 1). Port B Control Register 7 PBCR (0024H) Bit symbol Read/Write After reset Function 0 0: Input 1: Output 6 5 4 PB4C W 3 PB3C 0 2 1 0 Port B Function Register 7 PBFC (0025H) Bit symbol Read/Write After reset Function 0 0: Port 1: INT3 Note 1: Output latch register is set to 1. Note 2: Read-modify-write is prohibited for the registers PBCR and PBFC. Note 3: PB4/TA0IN pins do not have a register changing port/function . For example, when it is used as an input port, the input signal is inputted to 8-bit timer 0 as the timer input 0. 0 0: Port 1: INT2 6 PB6F 5 PB5F W 4 PB4F 0 0: Port 1: INT1 3 PB3F 1 0: Port 1: INT0 2 1 0 Figure 3.5.22 Registers for Port B 91C025-74 2007-02-28 TMP91C025 3.5.10 Port C (PC0 to PC5) Port C0 to C5 are 6-bit general-purpose I/O ports. Each bit can be set individually for input or output. Resetting sets PC0 to PC5 to be an input ports. It also sets all bits of the output latch register to 1. In addition to functioning as general-purpose I/O port pins, PC0 to PC5 can also function as the I/O for serial channels 0 and 1. A pin can be enabled for I/O by writing 1 to the corresponding bit of the port C function register (PCFC). Resetting resets all bits of the registers PCCR and PCFC to 0 and sets all pins to be input ports . (1) Port C0, C3 (TXD0/TXD1) As well as functioning as I/O port pins, port C0 and C3 can also function as serial channel TXD output pins. In case of use TXD0/TXD1, it is possible to logical invert by setting the register PC Reset Ditection control (on bit basis) PCCR write Function control Internal data bus (on bit basis) PCFC write S Output latch PC write TXD0, TXD1 Logical invert A S PC0 (TXD0) PC3 (TXD1) Open-drain set possible PCODE Selector B S PC Read B Selector A Figure 3.5.23 Port C0 and C3 91C025-75 2007-02-28 TMP91C025 (2) Port C1, C4 (RXD0, RXD1) Port C1 and C4 are I/O port pins and can also is used as RXD input for the serial channels. In case of use RXD0/RXD1, it is possible to logical invert by setting the register PC Reset Ditection control (on bit basis) Internal data bus PCCR write S Output latch PC write PC read RXD0, RXD1 Logical invert PC1 (RXD0) PC4 (RXD1) S B Selector A Figure 3.5.24 Port C1 and C4 (3) Port C2 ( CTS0 , SCLK0), C5 ( CTS1 , SCLK1) Port C2 and C5 are I/O port pins and can also is used as CTS input or SCLK input/output for the serial channels. In case of use CTS , SCLK, it is possible to logical invert by setting the register PC Reset Ditection control (on bit basis) PCCR write Internal data bus Function control (on bit basis) (Programmable pull-up) PCFC write S Output latch PC write SCLK0, 1 output PC2 (SCLK0, CTS0 ) PC5 (SCLK1, CTS1 ) A S Selector B Logical invert SB Selector PC read CTS0 , CTS1 SCLK0, SCLK 1 input A Logical invert Figure 3.5.25 Port C2 and C5 91C025-76 2007-02-28 TMP91C025 Port C Register 7 PC (0023H) Bit symbol Read/Write After reset 6 5 PC5 4 PC4 3 PC3 R/W 2 PC2 1 PC1 0 PC0 Data from external port (Output latch register is set to 1). Port C Control Register 7 PCCR (0026H) Bit symbol Read/Write After reset Function 0 0 0 0: Input 6 5 PC5C 4 PC4C 3 PC3C W 2 PC2C 0 1: Output 1 PC1C 0 0 PC0C 0 Port C Functon Register 7 PCFC (0027H) Bit symbol Read/Write After reset Function 6 5 PC5F W 0 0: Port 1: SCLK1 output 4 3 PC3F W 0 0: Port 1: TXD1 2 PC2F W 0 0: Port 1: SCLK0 output 1 0 PC0F W 0 0: Port 1: TXD0 Port C ODE Register 7 PCODE (0028H) Bit symbol Read/Write After reset Function 6 5 4 3 ODEPC3 W 0 TXD1 0: CMOS 1: Open drain 2 1 0 ODEPC0 W 0 TXD0 0: CMOS 1: Open drain Note 1: Note 2: Read-modify-write is prohibited for the registers PCCR, PCFC and PCODE. PC1/RXD0, PC4/RXD1 pins do not have a register changing port/function. For example, when it is used as an input port, the input signal is inputted to SIO as the cereal receive data. Figure 3.5.26 Registers for Port C 91C025-77 2007-02-28 TMP91C025 3.5.11 Port D (PD0 to PD4, PD7) Port D is a 6-bit output port. Resetting sets the output latch PD to "1", and PD0 to PD4, PD7 pin output "1". In addition to functioning as output port, port D also function as output pin for LCD controller (D1BSCP, D2BLP, D3BFR, DLEBCD and DOFFB) and output pin for melody/alarm generator (MLDALM). Above setting is used the function register PDFC. Reset Function control Internal data bus (on bit basis) PDFC write S Output latch Selector A B PD write D1BSCP, D2BLP, D3BFR, DLEBCD, DOFFB, MLDALM PD read Output buffer PD0 (D1BSCP), PD1 (D2BLP), PD2 (D3BFR), PD3 (DLEBCD), PD4 (DOFFB), PD7 (MLDALM) Figure 3.5.27 Port D Port D register 7 PD (0029H) Bit symbol Read/Write After reset PD7 R/W 1 6 5 4 PD4 R/W 1 3 PD3 R/W 1 2 PD2 R/W 1 1 PD1 R/W 1 0 PD0 R/W 1 Port D function register 7 PDFC (002AH) Bit symbol Read/Write After reset Function PD7F W 0 0: Port 1: MLDALM 6 5 4 PD4F W 0 0: Port 1: DOFFB 3 PD3F W 0 0: Port 1: DLEBCD 2 PD2F W 0 0: Port 1: D3BFR 1 PD1F W 0 0: Port 1: D2BLP 0 PD0F W 0 0: Port 1: D1BSCP Note: Read-modify-write is prohibited for the registers PDFC. Figure 3.5.28 Registers for Port D 91C025-78 2007-02-28 TMP91C025 3.6 Chip Select/Wait Controller On the TM91C025, four user-specifiable address areas (CS0 to CS3) can be set. The data bus width and the number of waits can be set independently for each address area (CS0 to CS3 and others). The pins CS0 to CS3 (which can also function as port pins P60 to P63) are the respective output pins for the areas CS0 to CS3. When the CPU specifies an address in one of these areas, the corresponding CS0 to CS3 pin outputs the chip select signal for the specified address area (in ROM or SRAM). However, in order for the chip select signal to be output, the port 6 function register P6FC must be set. CS2A to CS2C (CS pin except CS0 to CS3 ) are made by MMU. These pins is CS pin that area and BANK value is fixed without concern in setting of CS/WAIT controller. The areas CS0 to CS3 are defined by the values in the memory start address registers MSAR0 to MSAR3 and the memory address mask registers MAMR0 to MAMR3. The chip select/wait control registers B0CS to B3CS and BEXCS should be used to specify the master enable/disable status the data bus width and the number of waits for each address area. The input pin controlling these states is the bus wait request pin ( WAIT ). 3.6.1 Specifying an Address Area The CS0 to CS3 address areas are specified using the start address registers (MSAR0 to MSAR3) and memory address mask registers (MAMR0 to MAMR3). At each bus cycle, a compare operation is performed to determine if the address on the specified a location in the CS0 to CS3 area. If the result of the comparison is a match, this indicates an access to the corresponding CS area. In this case, the CS0 to CS3 pin outputs the chip select signal and the bus cycle operates in accordance with the settings in chip select/wait control register B0CS to B3CS. (See 3.6.2, Chip Select/Wait Control Registers.) 91C025-79 2007-02-28 TMP91C025 (1) Memory start address registers Figure 3.6.1 shows the memory start address registers. The memory start address registers MSAR0 to MSAR3 set the start addresses for the CS0 to CS3 areas. Set the upper 8 bits (A23 to A16) of the start address in MSAR0 (00C8H) MSAR2 (00CCH) MSAR1 (00CAH) MSAR3 (00CEH) Bit symbol Read/Write After reset Function 1 1 1 1 S23 6 S22 5 S21 4 S20 R/W 3 S19 1 2 S18 1 1 S17 1 0 S16 1 Determines A23 to A16 of start address. Sets start addresses for areas CS0 to CS3. Figure 3.6.1 Memory Start Address Register Start address Address 000000H 64 Kbytes Value in start address register (MSAR0 to MSAR3) 000000H ...................... 00H 010000H ...................... 01H 020000H ...................... 02H 030000H ...................... 03H 040000H ...................... 04H 050000H ...................... 05H 060000H ...................... 06H to to FF0000H ...................... FFH FFFFFFH Figure 3.6.2 Relationship between Start Address and Start Address Register Value 91C025-80 2007-02-28 TMP91C025 (2) Memory address mask registers Figure 3.6.3 shows the memory address mask registers. Memory address mask registers MAMR0 to MAMR3 are used to set the size of the CS0 to CS3 areas by specifying a mask for each bit of the start address set in memory start address registers MAMR0 to MAMR3. The compare operation used to determine if an address is in the CS0 to CS3 areas is only performed for bus address bits corresponding to bits set to 0 in these registers. Also, the address bits that can be masked by MAMR0 to MAMR3 differ between CS0 to CS3 areas. Accordingly, the size that can be each area is different. Memory Address Mask Register (for CS0 area) 7 MAMR0 (00C9H) Bit symbol Read/Write After reset Function 1 1 1 1 Sets size of CS0 area. V20 6 V19 5 V18 4 V17 R/W 3 V16 1 2 V15 1 1 V14 to 9 1 0 V8 1 0: Used for address compare Range of possible settings for CS0 area size: 256 bytes to 2 Mbytes Memory Address Mask Register (CS1) 7 MAMR1 (00CBH) Bit symbol Read/Write After reset Function 1 1 1 1 V21 6 V20 5 V19 4 V18 R/W 3 V17 1 2 V16 1 1 V15 to 9 1 0 V8 1 Sets size of CS1 area. 0: Used for address compare Range of possible settings for CS1 area size: 256 bytes to 4 Mbytes. Memory Address Mask Register (CS2, CS3) 7 MAMR2 (00CDH) MAMR3 (00CFH) Bit symbol Read/Write After reset Function 1 1 1 1 V22 6 V21 5 V20 4 V19 R/W 3 V18 1 2 V17 1 1 V16 1 0 V15 1 Sets size of CS2 or CS3 area. 0: Used for address compare Range of possible settings for CS2 and CS3 area sizes: 32 Kbytes to 8 Mbytes. Figure 3.6.3 Memory Address Mask Registers 91C025-81 2007-02-28 TMP91C025 (3) Setting memory start addresses and address areas Figure 3.6.4 show an example of specifying a 64-Kbyte address area starting from 010000H using the CS0 areas. Set 01H in memory start address register MSAR0 0 0 0 0 0 0 0 1 0 1 1 1 F 1 1 1 1 F 1 1 1 1 F 1 1 1 1 F 1 1 H Memory end address S23 S22 S21 S20 S19 S18 S17 S16 CSO area size (64 Kbytes) MSAR0 0 0 0 0 0 0 0 1 0 1 H Memory start address V20 V19 V18 V17 V16 V15 V14 V9 V8 MSMR0 0 0 0 0 0 0 0 0 0 1 1 1 1 7 1 1 1 1 1 H 1 1 1 1 1 1 1 Memory address mask register setting Setting of 07H specifies a 64-Kbyte area. Figure 3.6.4 Example Showing How to Set the CS0 Area After a reset, MSAR0 to MSAR3 and MAMR0 to MAMR3 are set to FFH. B0CS 91C025-82 2007-02-28 TMP91C025 (4) Address area size specification Table 3.6.1 shows the relationship between CS area and area size. Triangle () indicates areas that cannot be set by memory start address register and address mask register combinations. When setting an area size using a combination indicated by , set the start address mask register in the desired steps starting from 000000H. If the CS2 area is set to 16 Mbytes or if two or more areas overlap, the smaller CS area number has the higher priority. Example: To set the area size for CS0 to 128 Kbytes: (a) Valid start addresses 000000H 020000H 040000H 060000H 128 Kbytes 128 Kbytes 128 Kbytes Any of these addresses may be set as the start address. (b) Invalid start addresses 000000H 010000H 030000H 050000H 64 Kbytes 128 Kbytes 128 Kbytes This is not an integer multiple of the desired area size setting. Hence, none of these addresses can be set as the start address. Table 3.6.1 Valid Area Sizes for Each CS Area Size (Bytes) CS Area 256 512 32 K 64 K 128 K 256 K 512 K 1M 2M 4M 8M CS0 CS1 CS2 CS3 Note: : This symbol indicates areas that cannot be set by memory start address register and address mask register combinations. 3.6.2 Chip Select/Wait Control Registers Figure 3.6.5 lists the chip select/wait control registers. The master enable/disable, chip select output waveform, data bus width and number of wait states for each address area (CS0 to CS3 and others) are set in their respective chip select/wait control registers, B0CS to B3CS and BEXCS. 91C025-83 2007-02-28 TMP91C025 7 B0CS (00C0H) Bit symbol Read/Write After reset Function B0E W 0 0: Disable 1: Enable 6 5 B0OM1 0 4 B0OM0 0 3 B0BUS W 0 Data bus width 0: 16 bits 1: 8 bits 2 B0W2 0 Number of waits 000: 2 waits 001: 1 wait 010: (1 + N) waits 011: 0 waits 1 B0W1 0 0 B0W0 0 Chip select output waveform selection. 00: For ROM/SRAM 01: 10: Don't care 11: 100: (0 + N) waits 101: 3 waits 110: 4 waits 111: 8 waits B1CS (00C1H) Bit symbol Read/Write After reset Function B1E W 0 0: Disable 1: Enable B1OM1 0 B1OM0 0 B1BUS W 0 Data bus width 0: 16 bits 1: 8 bits B1W2 0 B1W1 0 B1W0 0 Chip select output waveform selection. 00: For ROM/SRAM 01: 10: Don't care 11: Number of waits 000: 2 waits 001: 1 wait 010: (1 + N) waits 011: 0 waits 100: (0 + N) waits 101: 3 waits 110: 4 waits 111: 8 waits B2CS (00C2H) Bit symbol Read/Write After reset Functions B2E 1 0: Disable 1: Enable B2M 0 CS2 area selection. 0: 16-Mbyte area 1: CS area B2OM1 0 B2OM0 W 0 B2BUS 0 Data bus width 0: 16 bits 1: 8 bits B2W2 0 B2W1 0 B2W0 0 Chip select output waveform selection. 00: For ROM/SRAM 01: 10: Don't care 11: Number of waits 000: 2 waits 001: 1 wait 010: (1 + N) waits 011: 0 waits 100: (0 + N) waits 101: 3 waits 110: 4 waits 111: 8 waits B3CS (00C3H) Bit symbol Read/Write After reset Functions B3E W 0 0: Disable 1: Enable B3OM1 0 B3OM0 0 B3BUS W 0 Data bus width 0: 16 bits 1: 8 bits B3W2 0 B3W1 0 B3W0 0 Chip select output waveform selection. 00: For ROM/SRAM 01: 10: Don't care 11: Number of waits 000: 2 waits 001: 1 wait 010: (1 + N) waits 011: 0 waits 100: (0 + N) waits 101: 3 waits 110: 4 waits 111: 8 waits BEXCS (00C7H) Bit symbol Read/Write After reset Functions BEXBUS 0 Data bus width 0: 16 bits 1: 8 bits BEXW2 W 0 BEXW1 0 BEXW0 0 Number of waits 000: 2 waits 001: 1 wait 010: (1 + N) waits 011: 0 waits 100: (0 + N) waits 101: 3 waits 110: 4 waits 111: 8 waits Master enable bit 0 1 Disable Enable Chip select output waveform selection Number of address area waits (See 3.6.2, (3) Wait control.) Data bus width selection 00 For ROM/SRAM 01 10 Don't care 11 CS2 area selection 0 1 16-Mbyte area Specified address area 0 1 16-bit data bus 8-bit data bus Note: Read-modify-write is prohibited for the registers B0CS, B1CS, B2CS, B3CS and BEXCS. Figure 3.6.5 Chip Select/Wait Control Registers 91C025-84 2007-02-28 TMP91C025 (1) Master enable bits Bit 7 ( 91C025-85 2007-02-28 Operand D15 to D8 D7 to D0 b7-b0 L XXXX b7-b0 b7-b0 XXXX b7-b0 b15-b8 b7-b0 b7-b0 b15-b8 XXXX H L L H H b15-b8 b7-b0 b15-b8 b23-b16 b31-b24 b7-b0 b23-b16 b7-b0 b15-b8 b23-b16 b31-b24 XXXX b15-b8 b31-b24 H L L L L H H L L L L H H L L L L H L L L H L L L H L L L H L H L H L H H L H L H H L H L L L H H L L H L H L L L H L H L H L H L H L H L L L H L H L H L H L H XXXX b7-b0 XXXX XXXX b15-b8 XXXX XXXX b7-b0 XXXX XXXX XXXX XXXX XXXX b15-b8 b31-b24 XXXX XXXX XXXX XXXX b7-b0 b23-b16 XXXX H L H L H RD WR HWR SRLB SRUB SRWR RD WR HWR XXXX R/W R/W SRLB Operand Memory Data Bus Start Data Bus CPU CPU Data Control for READ Cycle Control for WRITE Cycle SRUB SRWR Width Address Width Address 2n + 0 8 bits 2n + 0 (Even number) 16 bits 2n + 0 8 bits 2n + 1 8 bits 2n + 1 (Odd number) 16 bits 2n + 1 2n + 0 8 bits 2n + 0 (Even 2n + 1 number) 16 bits 2n + 0 Table 3.6.2 Dynamic Bus Sizing these bits goes too high-impedance; also, that the write strobe signal for the bus remains inactive. xxxx: Indicates that the input data from these bits are ignored during a read. During a write, indicates that the bus for 91C025-86 16 bits 2n + 1 (Odd 8 bits 2n + 1 2n + 2 number) 16 bits 2n + 1 L 2n + 2 2n + 0 2n + 0 8 bits 2n + 1 (Even 2n + 2 number) 2n + 3 16 bits 2n + 0 2n + 2 32 bits 2n + 1 8 bits 2n + 2 2n + 1 (Odd 2n + 3 number) 2n + 4 16 bits 2n + 1 2n + 2 TMP91C025 2007-02-28 2n + 4 TMP91C025 (3) Wait control Bits 0 to 2 ( 000 001 010 No. of Waits 2 waits 1 wait (1 + N) waits Wait Operation Inserts a wait of 2 states, irrespective of the WAIT pin state. Inserts a wait of 1 state, irrespective of the WAIT pin state. Samples the state of the WAIT pin after inserting a wait of one state. If the WAIT pin is low, the waits continue and the bus cycle is extended until the pin goes high. 011 100 0 waits (0 + N) waits Ends the bus cycle without a wait, regardless of the WAIT pin state. Samples the state of the WAIT pin without inserting a wait. If the WAIT pin is low, the waits continue and the bus cycle is extended until the pin goes high. 101 110 111 3 waits 4 waits 8 waits Inserts a wait of 3 states, irrespective of the WAIT pin state. Inserts a wait of 4 states, irrespective of the WAIT pin state. Inserts a wait of 8 states, irrespective of the WAIT pin state. A Reset sets these bits to 000 (2 waits). 375 ns 62.5 ns fFPH T1 TW (at 16 MHz) T2 CSn R/ W A0 to A23 D0 to D15 Data-in Read RD D0 to D15 Data-out Write HWR , WR WAIT Figure 3.6.6 (0 + N) Waits Read/Write Cycle (N = 1) 91C025-87 2007-02-28 TMP91C025 (4) Bus width and wait control for an area other than CS0 to CS3 The chip select/wait control register BEXCS controls the bus width and number of waits when memory locations which are not in one of the four user-specified address areas (CS0 to CS3) are accessed. The BEXCS register settings are always enabled for areas other than CS0 to CS3. (5) Selecting 16-Mbyte area/specified address area Setting B2CS (Setting example) In this example CS0 is set to be the 64-Kbyte area 010000H to 01FFFFH. The bus width is set to 16 bits and the number of waits is set to 0. MSAR0 = 01H MAMR0 = 07H B0CS = 83H Start address: 010000H Address area: 64 Kbytes ROM/SRAM, 16-bit data bus, zero waits, CS0 area settings enabled. 91C025-88 2007-02-28 TMP91C025 3.6.3 Connecting External Memory Figure 3.6.7 shows an example of how to connect external memory to the TMP91C025. In this example the ROM is connected using a 16-bit bus. The RAM and I/O are connected using an 8-bit bus. TMP91C025 CS0 CS1 CS2 Address bus CS Upper byte ROM OE CS Lower byte ROM OE CS CS A0 to A23 D8 to D15 D0 to D7 RD WR 8-bit RAM OE WE 8-bit I/O OE WE Figure 3.6.7 Example of External Memory Connection (ROM uses 16-bit bus: RAM and I/O use 8-bit bus.) A reset clears all bits of the port 6 control register P6CR and the port 6 function register P6FC to 0 and disables output of the CS signal. To output the CS signal, the appropriate bit must be set to 1. 91C025-89 2007-02-28 TMP91C025 TMP91C025 RD 16-bit SRAM OE LDS UDS SRLB SRUB SRWR CS0 R/ W CE D [15:0] A0 A1 A2 A3 Not connect I/O [16:1] A0 A1 A2 Figure 3.6.8 How to Connect to 16-Bit SRAM for TMP91C025 91C025-90 2007-02-28 TMP91C025 3.7 8-Bit Timers (TMRA) The TMP91C025 features 4 channel (TMRA0 to TMRA3) built-in 8-bit timers. These timers are paired into 2 modules: TMRA01 and TMRA23. Each module consists of 2 channels and can operate in any of the following 4 operating modes. * * * * 8-bit interval timer mode 16-bit interval timer mode 8-bit programmable square wave pulse generation output mode (PPG: Variable duty cycle with variable period) 8-bit pulse width modulation output mode (PWM: Variable duty cycle with constant period) Figure 3.7.1 to Figure 3.7.2 Show block diagrams for TMRA01 and TMRA23. Each channel consists of an 8-bit up counter, an 8-bit comparator and an 8-bit timer register. In addition, a timer flip-flop and a prescaler are provided for each pair of channels. The operation mode and timer flip-flops are controlled by 5 bytes registers SFRs (Special-function registers). Each of the 2 modules (TMRA01 and TMRA23) can be operated independently. All modules operate in the same manner; hence only the operation of TMRA01 is explained here. The contents of this chapter are as follows. 3.7.1 3.7.2 3.7.3 3.7.4 Block Diagrams Operation of Each Circuit SFRs Operation in Each Mode (1) 8-bit timer mode (2) 16-bit timer mode (3) 8-bit PPG (Programmable pulse generation) output mode (4) 8-bit PWM (Pulse width modulation) output mode (5) Setting for each mode Table 3.7.1 Registers and Pins for Each Module Module Input pin for external External pin clock Output pin for timer flip-flop Timer run register SFR Timer register TMRA01 TA0IN (shared with PB4) TA1OUT (shared with PA1) TA01RUN (0100H) TA0REG (0102H) TA1REG (0103H) TA01MOD (0104H) TA1FFCR (0105H) TMRA23 None TA3OUT (shared with PA2) TA23RUN (0108H) TA2REG (010AH) TA3REG (010BH) TA23MOD (010CH) TA3FFCR (010DH) (address) Timer mode register Timer flip-flop control register 91C025-91 2007-02-28 3.7.1 Prescaler 2 4 8 16 32 64 128 256 512 Prescaler clock: T0 n Block Diagrams Run/clear TA01RUN TA01RUN Timer flip-flop output: TA1OUT External input clock: TA0IN T1 T4 T16 TA01MOD Figure 3.7.1 TMRA01 Block Diagram 91C025-92 8-bit compatator (CP0) TA0TR TA01MOD Match 8-bit comparator detect (CP1) 8-bit timer register TA1REG TMP91C025 TMRA0 Internal data bus TMRA1 match output: interrupt output: TA0TRG INTTA1 2007-02-28 Prescaler Prescaler clock: T0 2 T1 T4 T16 T256 Timer flip-flop TA3FF TA23RUN n 4 8 16 32 64 128 256 512 Run/clear TA23RUN TA23RUN T1 T4 T16 T1 T16 T256 Timer flip-flop output: TA3OUT Possible to connect to LCD and MLD circuits Figure 3.7.2 TMRA23 Block Diagram TA23MOD 91C025-93 Match 8-bit comparator detect (CP2) TA2TRG TA23MOD Match 8-bit comparator detect register (CP3) 8-bit timer register TA3REG TMRA2 Internal data bus TMRA3 match output: interrup output: TA2TRG INTTA3 TMP91C025 2007-02-28 TMP91C025 3.7.2 Operation of Each Circuit (1) Prescalers A 9-bit prescaler generates the input clock to TMRA01. The T0 as the input clock to prescaler is a clock divided by 4 which selected using the prescaler clock selection register SYSCR0 Table 3.7.2 Prescaler Output Clock Resolution at fc = 36 MHz, fs = 32.768 kHz System Clock Selection SYSCR1 1 (fs) Prescaler Clock Selection SYSCR0 Gear Value SYSCR1 XXX 000 (fc) 3 Prescaler Output Clock Resolution T1 2 /fs (244 s) 2 /fc (0.2 s) 3 4 5 6 7 7 5 T4 2 /fs (977 s) 2 /fc (0.9 s) 5 6 7 8 7 T16 11 T256 2 /fs (3.9 ms) 2 /fs (62.5 ms) 2 /fc (3.6 s) 7 8 9 2 /fc (56.9 s) 11 12 13 14 15 15 00 0 (fc) (fFPH) 001 (fc/2) 010 (fc/4) 011 (fc/8) 100 (fc/16) 2 /fc (0.4 s) 2 /fc (0.9 s) 2 /fc (1.8 s) 2 /fc (3.6 s) 2 /fc (3.6 s) 2 /fc (1.8 s) 2 /fc (3.6 s) 9 9 2 /fc (7.1 s) 2 /fc (113.8 s) 2 /fc (14.2 s) 2 /fc (227.6 s) 10 11 11 2 /fc (7.1 s) 2 /fc (28.4 s) 2 /fc (455.1 s) 2 /fc (14.2 s) 2 /fc (56.9 s) 2 /fc (910.2 s) 2 /fc (14.2 s) 2 /fc (56.9 s) 2 /fc (910.2 s) 10 (fc/16 CLOCK) XXX xxx: Don't care (2) Up counters (UC0 and UC1) These are 8-bit binary counters which count up the input clock pulses for the clock specified by TA01MOD. The input clock for UC0 is selectable and can be either the external clock input via the TA0IN pin or one of the three internal clocks T1, T4 or T16. The clock setting is specified by the value set in TA01MOD 91C025-94 2007-02-28 TMP91C025 (3) Timer registers (TA0REG and TA1REG) These are 8-bit registers which can be used to set a time interval. When the value set in the timer register TA0REG or TA1REG matches the value in the corresponding up counter, the comparator match detect signal goes active. If the value set in the timer register is 00H, the signal goes active when the up counter overflows. The TA0REG are double buffer structure, each of which makes a pair with register buffer. The setting of the bit TA01RUN Timer registers 0 (TA0REG) Y Shift trigger Register buffers 0 Write Internal data bus Selector B Matching detection in PPG cycle n 2 overflow of PWM Write to TA0REG A S TA01RUN Figure 3.7.3 Configuration of TA0REG Note: The same memory address is allocated to the timer register and the register buffer. When All these registers are write only and cannot be read. 91C025-95 2007-02-28 TMP91C025 (4) Comparator (CP0) The comparator compares the value in an up counter with the value set in a timer register. If they match, the up counter is cleared to zero and an interrupt signal (INTTA0 or INTTA1) is generated. If timer flip-flop inversion is enabled, the timer flip-flop is inverted at the same time. (5) Timer flip-flop (TA1FF) The timer flip-flop (TA1FF) is a flip-flop inverted by the match detects signal (8-bit comparator output) of each interval timer. Whether inversion is enabled or disabled is determined by the setting of the bit TA1FFCR Match between TA0REG and up-counter 2 overflow interrupt (INTTA0) TA1OUT tPWM (PWM cycle) n Desired PWM cycle change point Write new data to the register buffer before the next overflow occurs by using an overflow interrupt 91C025-96 2007-02-28 TMP91C025 3.7.3 SFRs TMRA01 Run Register 7 TA01RUN (0100H) Bit symbol Read/Write After reset Function TA0RDE R/W 0 Double buffer 0: Disable 1: Enable TA0REG double buffer control 0 1 Disable Enable Timer run/stop control 0 1 Stop and clear Run (Count up) 0 IDLE2 0: Stop 0 0: Stop and clear 6 5 4 3 I2TA01 2 TA01PRUN 1 TA1RUN 0 R/W 0 TA0RUN 0 8-bit timer run/stop control 1: Operate 1: Run (Count up) I2TA01: TA01PRUN: TA1RUN: TA0RUN: Note: The values of bits 4, 5, 6 of TA01RUN are undefined when read. Operation in IDLE2 mode Run prescaler Run TMRA1 Run TMRA0 TMRA23 Run Register 7 TA23RUN (0108H) Bit symbol Read/Write After reset Function TA2RDE R/W 0 Double buffer 0: Disable 1: Enable TA2REG double buffer control 0 1 Disable Enable I2TA23: TA23PRUN: TA3RUN: TA2RUN: Note: The values of bits 4, 5, 6 of TA23RUN are undefined when read. Timer run/stop control 0 1 Stop and clear Run (Count up) 0 IDLE2 0: Stop 0 0: Stop and clear 6 5 4 3 I2TA23 2 TA23PRUN 1 TA3RUN 0 R/W 0 TA2RUN 0 8-bit timer run/stop control 1: Operate 1: Run (Count up) Operation in IDLE2 mode Run prescaler Run TMRA3 Run TMRA2 Figure 3.7.4 TMRA Registers 91C025-97 2007-02-28 TMP91C025 TMRA01 Mode Register TA01MOD (0104H) 7 Bit symbol Read/Write After reset Function 0 Operation mode TA01M1 6 TA01M0 0 5 PWM01 0 PWM cycle 00: Reserved 01: 2 6 7 8 4 PWM00 0 R/W 3 TA1CLK1 0 00: TA0TRG 01: T1 10: T16 11: T256 2 TA1CLK0 0 1 TA0CLK1 0 00: TA0IN pin 01: T1 10: T4 11: T16 0 TA0CLK0 0 Source clock for TMRA1 Source clock for TMRA0 00: 8-bit timer mode 01: 16-bit timer mode 10: 8-bit PPG mode 11: 8-bit PWM mode 10: 2 11: 2 TMRA0 source clock selection 00 01 10 11 TA0IN (External input) T1 (Prescaler) T4 (Prescaler) T16 (Prescaler) TMRA1 source clock selection TA01MOD 00 01 10 11 Comparator output from TMRA0 T1 T16 T256 Overflow output from TMRA0 (16-bit timer mode) PWM cycle selection 00 01 10 11 Reserved 2 x source clock 6 7 8 2 x source clock 2 x source clock TMRA01 operation mode selection 00 01 10 11 Two 8-bit timers 16-bit timer 8-bit PPG 8-bit PWM (TMRA0) + 8-bit timer (TMRA1) Figure 3.7.5 TMRA Registers 91C025-98 2007-02-28 TMP91C025 TMRA23 Mode Register 7 TA23MOD (010CH) Bit Symbol Read/Write After reset Function 0 Operation mode 00: 8-bit timer mode 01: 16-bit timer mode 10: 8-bit PPG mode 11: 8-bit PWM mode 0 0 PWM cycle 00: Reserved 01: 2 6 7 8 6 TA23M0 5 PWM21 4 PWM20 0 R/W 3 TA3CLK1 0 00: TA2TRG 01: T1 10: T16 11: T256 2 TA3CLK0 0 1 TA2CLK1 0 00: Reserved 01: T1 10: T4 11: T16 0 TA2CLK0 0 TA23M1 TMRA3 clock for TMRA3 TMRA2 clock for TMRA2 10: 2 11: 2 TMRA2 source clock selection 00 01 10 11 Do not set T1 (Prescaler) T4 (Prescaler) T16 (Prescaler) TMRA3 source clock selection TA23MOD PWM cycle selection 00 01 10 11 Reserved 2 x source clock 6 7 8 2 x source clock 2 x source clock TMRA23 operation mode selection 00 01 10 11 Two 8-bit timers 16-bit timer 8-bit PPG 8-bit PWM (TMRA2) + 8-bit timer (TMRA3) Figure 3.7.6 TMRA Registers 91C025-99 2007-02-28 TMP91C025 TMRA1 Flip-Flop Control Register 7 TA1FFCR (0105H) Bit symbol Read/Write After reset Function Read-modify -write instructions are prohibited. 6 5 4 3 TA1FFC1 1 00: Invert TA1FF 01: Set TA1FF 10: Clear TA1FF 11: Don't care R/W 2 TA1FFC0 1 1 TA1FFIE 0 TA1FF control for inversion 0: Disable 1: Enable R/W 0 TA1FFIS 0 TA1FF inversion select 0: TMRA0 1: TMRA1 Inverse signal for timer flop-flop 1 (TA1FF) (Don't care except in 8-bit timer mode) 0 1 Inversion by TMRA0 Inversion by TMRA1 Inversion of TA1FF 0 1 Disabled Enabled Control of TA1FF 00 01 10 11 Inverts the value of TA1FF Sets TA1FF to 1 Clears TA1FF to 0 Don't care Figure 3.7.7 TMRA Registers 91C025-100 2007-02-28 TMP91C025 TMRA3 Flip-Flop Control Register 7 TA3FFCR (010DH) Bit symbol Read/Write After reset Function Read-modify -write instructions are prohibited. 6 5 4 3 TA3FFC1 1 00: Invert TA3FF 01: Set TA3FF 10: Clear TA3FF 11: Don't care R/W 2 TA3FFC0 1 1 TA3FFIE 0 TA3FF control for inversion 0: Disable 1: Enable R/W 0 TA3FFIS 0 TA3FF inversion select 0: TMRA2 1: TMRA3 Inverse signal for timer flip-flop 3 (TA3FF) (Don't care except in 8-bit timer mode) 0 1 Inversion by TMRA2 Inversion by TMRA3 Inversion of TA3FF 0 1 Disabled Enabled Control of TA3FF 00 01 10 11 Inverts the value of TA3FF Sets TA3FF to 1 Clears TA3FF to 0 Don't care Figure 3.7.8 TMRA Registers 91C025-101 2007-02-28 TMP91C025 TMRA register 7 TA0REG (0102H) TA1REG (0103H) TA2REG (010AH) TA3REG (010BH) bit Symbol Read/Write After reset bit Symbol Read/Write After reset bit Symbol Read/Write After reset bit Symbol Read/Write After reset 6 5 4 - W Undefined - W Undefined - W Undefined - W Undefined 3 2 1 0 Note: The above registers are prohibited read-modify-write instruction. Figure 3.7.9 TMRA Registers 91C025-102 2007-02-28 TMP91C025 3.7.4 Operation in Each Mode (1) 8-bit timer mode Both TMRA0 and TMRA1 can be used independently as 8-bit interval timers. Setting its function or counter data for TMRA0 and TMRA1 after stop these registers. a. Generating interrupts at a fixed interval (Using TMRA1) To generate interrupts at constant intervals using TMRA1 (INTTA1), first stop TMRA1 then set the operation mode, input clock and a cycle to TA01MOD and TA1REG register, respectively. Then, enable the interrupt INTTA1 and start TMRA1 counting. Example: To generate an INTTA1 interrupt every 8.0 s at fc = 36 MHz, set each register as follows: Clock state System clock: High-frequency (fc) Prescaler clock: fFPH MSB 7 TA01RUN TA01MOD TA1REG INTETA01 TA01RUN - 0 0 X - 6 X 0 0 1 X 5 X X 1 0 X 4 X X 0 1 X 3 - 0 1 - - 2 - 1 0 - 1 1 0 X 0 - 1 LSB 0 - X 0 - - Stop TMRA1 and clear it to 0. Select 8-bit timer mode and select T1 ((2 /fc)s at fc = 36 MHz) as the input clock. 3 Set TA1REG to 8.0 s / T1(2 /fc) 40 = 28H 3 Enable INTTA1 and set it to level 5. Start TMRA1 counting. X: Don't care, -: No change Select the input clock using Table 3.7 2. Note: The input clocks for TMRA0 and TMRA1 are different from as follows. TMRA0: TA0IN input, T1, T4 or T16 TMRA1: Match output of TMRA0, T1, T16, T256 91C025-103 2007-02-28 TMP91C025 b. Generating a 50% duty ratio square wave pulse The state of the timer flip-flop (TA1FF) is inverted at constant intervals and its status output via the timer output pin (TA1OUT). Example: To output a 1.2-s square wave pulse from the TA1OUT pin at fc = 36 MHz, use the following procedure to make the appropriate register settings. This example uses TMRA1; however, either TMRA0 or TMRA1 may be used. Clock state System clock: High-frequency (fc) Clock gear: 1 (fc) Prescaler clock: fFPH 7 TA01RUN TA01MOD TA1REG TA1FFCR PAFC2 TA01RUN - 0 0 X X - 6 X 0 0 X X X 5 X X 0 X X X 4 X X 0 X X X 3 - 0 0 1 - - 2 - 1 0 0 - 1 1 0 - 1 1 1 1 0 - - 1 1 - - Stop TMRA1 and clear it to 0. Select 8-bit timer mode and select T1 ((2 /fc)s at fc = 36 3 MHz) as the input clock. Set the timer register to 1.2 s / T1(2 /fc) / 2 = 3 3 Clear TA1FF to 0 and set it to invert on the match detects signal from TMRA1. Set PA1 to function as the TA1OUT pin. Start TMRA1 counting. X: Don't care, -: No change T1 TA01RUN 0 1 2 3 0 1 2 3 0 1 2 3 0 TA1FF TA1OUT 0.6 s at fc = 36 MHz Figure 3.7.10 Square Wave Output Timing Chart (50% duty) 91C025-104 2007-02-28 TMP91C025 c. Making TMRA1 count up on the match signal from the TMRA0 comparator Select 8-bit timer mode and set the comparator output from TMRA0 to be the input clock to TMRA1. Comparaot output (TMRA0 match) TMRA0 up counter (when TA0REG = 5) TMRA1 up counter (when TA1REG = 2) TMRA1 match output 1 2 3 1 4 5 1 2 3 2 4 5 1 2 1 3 Figure 3.7.11 TMRA1 Count Up on Signal from TMRA0 91C025-105 2007-02-28 TMP91C025 (2) 16-bit timer mode A 16-bit interval timer is configured by pairing the two 8-bit timers TMRA0 and TMRA1. To make a 16-bit interval timer in which TMRA0 and TMRA1 are cascaded together, set TA01MOD Clock state System clock: High-frequency (fc) Clock gear: 1 (fc) Prescaler clock: fFPH If T16 ((27/fc)s at 36 MHz) is used as the input clock for counting, set the following value in the registers: 0.22 s/(27/fc) s 62500 = F424H (i.e. set TA1REG to F4H and TA0REG to 24H). As a result, INTTA1 interrupt can be generated every 0.23 [s]. The comparator match signal is output from TMRA0 each time the up counter UC0 matches TA0REG, though the up counter UC0 is not be cleared and also INTTA0 is not generated. In the case of the TMRA1 comparator, the match detect signal is output on each comparator pulse on which the values in the up counter UC1 and TA1REG match. When the match detect signal is output simultaneously from both the comparators TMRA0 and TMRA1, the up counters UC0 and UC1 are cleared to 0 and the interrupt INTTA1 is generated. Also, if inversion is enabled, the value of the timer flip-flop TA1FF is inverted. (Example) When TA1REG = 04H and TA0REG = 80H Value of up counter (UC1, UC0) TMRA0 comparator match detect signal TMRA0 comparator match detect signal INTTA0 INTTA1 TA1OUT 0080H 0180H 0280H 0380H 0480H 0080H Inversion Figure 3.7.12 Timer Output by 16-Bit Timer Mode 91C025-106 2007-02-28 TMP91C025 (3) 8-bit PPG (Programmable pulse generation) output mode Square wave pulses can be generated at any frequency and duty ratio by TMRA0. The output pulses may be active low or active high. In this mode TMRA1 cannot be used. TMRA0 outputs pulses on the TA1OUT pin. tH When tL tH Example when Figure 3.7.13 8-Bit PPG Output Waveforms 91C025-107 2007-02-28 TMP91C025 In this mode, a programmable square wave is generated by inverting the timer output each time the 8-bit up counter (UC0) matches the value in one of the timer registers TA0REG or TA1REG. The value set in TA0REG must be smaller than the value set in TA1REG. Although the up counter for TMRA1 (UC1) is not used in this mode, TA01RUN TA1OUT TA0IN T1 T4 T16 Selector TA01RUN Inversion INTTA0 Comparator INTTA1 TA01MOD Comparator Selector TA0REG-WR TA0REG Shift trigger Register buffer TA1REG TA01RUN Figure 3.7.14 Block Diagram of 8-Bit PPG Output Mode If the TA0REG double buffer is enabled in this mode, the value of the register buffer will be shifted into TA0REG each time TA1REG matches UC0. Use of the double buffer facilitates the handling of low-duty waves (when duty is varied). Match with TA0REG Match with TA1REG TA0REG (Value to be compared) Register buffer Q1 Q2 Shift from register buffer Q2 Q3 TA0REG (Register buffer) write (Up counter = Q1) (Up countner = Q2) Figure 3.7.15 Operation of Register Buffer 91C025-108 2007-02-28 TMP91C025 (Example) To generate 1/4-duty 50 kHz pulses (at fc = 36 MHz): 20 s Clock state System clock: High-frequency (fc) Clock gear: 1 (fc) Prescaler clock: fFPH Calculate the value which should be set in the timer register. To obtain a frequency of 50 kHz, the pulse cycle t should be: t = 1/50 kHz = 20 s T1 = (23/fc)s (at 36 MHz); 20 s / (23/fc)s 90 Therefore set TA1REG to 90 (5AH) The duty is to be set to 1/4: t x 1/4 = 20 s x 1/4 = 5 s 5 s / (23/fc)s 22 Therefore, set TA0REG = 22 = 16H. 7 TA01RUN TA01MOD TA0REG TA1REG TA1FFCR PAFC2 TA01RUN 0 1 0 0 X X 1 6 X 0 0 1 X X X 5 X X 0 0 X X X 4 X X 1 1 X X X 3 - X 0 1 0 - - 2 0 X 1 0 1 - 1 1 0 0 1 1 1 1 1 0 0 1 0 0 X - 1 Stop TMRA0 and TMRA0, 1 and clear it to 0. Set the 8-bit PPG mode, and select T1 as input clock. Write 16H Write 5AH Set TA1FF, enabling both inversion and the double buffer. Writing 10 provides negative logic pulse. Set PA1 as the TA1OUT pin. Start TMRA0 and TMRA01 counting. X: Don't care, -: No change 91C025-109 2007-02-28 TMP91C025 (4) 8-bit PWM (Pulse width modulation) output mode This mode is only valid for TMRA0. In this mode, a PWM pulse with the maximum resolution of 8 bits can be output. When TMRA0 is used the PWM pulse is output on the TA1OUT pin (which is also used as P71). TMRA1 can also be used as an 8-bit timer. The timer output is inverted when the up counter (UC0) matches the value set in the timer register TA0REG or when 2n counter overflow occurs (n = 6, 7 or 8 as specified by TA01MOD TA0REG and UC0 match 2 overflow (INTTA0 interrupt) TA1OUT tPWM (PWM cycle) n Figure 3.7.16 8-Bit PWM Waveforms TA01RUN TA0IN T1 T4 T16 TA1OUT TA1FFCR Selector 8-bit up counter (UC0) Clear 2 n TAFF1 Invert TA01MOD TA01MOD overflow control Overflow Comparator INTTA0 TA0REG Selector TA0REG-WR Shift trigger Register buffer TA01RUN Figure 3.7.17 Block Diagram of 8-Bit PWM Mode 91C025-110 2007-02-28 TMP91C025 In this mode, the value of the register buffer will be shifted into TA0REG if 2n overflow is detected when the TA0REG double buffer is enabled. Use of the double buffer facilitates the handling of low duty ratio waves. Match with TA0REG Up counter = Q1 2 overflow TA0REG (value to be compared) Register buffer Q1 Q2 Shift into TA0REG Q2 Q3 TA0REG (Register buffer) write n Up counter = Q2 Figure 3.7.18 Register Buffer Operation Example: To output the following PWM waves on the TA1OUT pin at fc = 16 MHz: 16.0 s 28.4 s Clock state System clock: High-frequency (fc) Clock gear: 1 (fc) Prescaler clock: fFPH To achieve a 64.0-s PWM cycle by setting T1 to (23/fc)s (at fc = 36 MHz): 28.4 s / (23/fc)s 128 = 2n Therefore n should be set to 7. Since the low-level period is 16.0 sec when T1 = (23/fc)s, set the following value for TA0REG: 16.0 s / (23/fc)s 72 = 48H MSB 7 TA01RUN TA01MOD TA0REG TA1FFCR PAFC2 TA01RUN - 1 0 X X 1 6 X 1 1 X X X 5 X 1 0 X X X 4 X 0 0 X X X LSB 3 - - 1 1 - - 2 - - 0 0 - 1 1 - 0 0 1 1 - 0 0 1 0 X - 1 Stop TMRA0 and clear it to 0. Select 8-bit PWM mode (cycle: 2 ) and select T1 as the 7 input clock. Write 48H. Clear TA1FF to 0, enable the inversion and double buffer. Set PA1 and the TA1OUT pin. Start TMRA0 counting. X: Don't care, -: No change 91C025-111 2007-02-28 TMP91C025 Table 3.7.3 PWM Cycle at fc = 36 MHz, fs = 32.768 kHz Select System Select Prescaler Clock SYSCR1 00 (fFPH) PWM Cycle 2 T1 15.6 ms 14.2 s 28.4 s 56.8 s 113 s 227 s 227 s 6 27 T16 250 ms 227 s 455 s 910 s 1820 s 3640 s 3640 s 28 T16 500 ms 455 s 910 s 1820 s 3640 s 7281 s 7281 s T4 62.5 ms 56.8 s 113 s 227 s 455 s 910 s 910 s T1 31.3 ms 28.4 s 56.8 s 113 s 227 s 455 s 455 s T4 125 ms 113 s 227 s 455 s 910 s 1820 s 1820 s T1 62.5 ms 56.8 s 113 s 227 s 455 s 910 s 910 s T4 250 ms 227 s 455 s 910 s 1820 s T16 1000 ms 910 s 1820 s 3640 s 7281 s 001 (fc/2) 010 (fc/4) 011 (fc/8) 100 (fc/16) 0 (fc) 3640 s 14563 s 3640 s 14563 s 10 (fc/16 clock) XXX XXX: Don't care (5) Settings for each mode Table 3.7.4 shows the SFR settings for each mode. Table 3.7.4 Timer Mode Setting Registers Register Name 8-bit timer x 2 channels TA01MOD - TA1FFCR TA1FFIS Timer F/F Invert Signal Select 0: Lower timer output 1: Upper timer output Upper Timer Input Clock Lower timer match T1, T16, T256 (00, 01, 10, 11) Lower Timer Input Clock External clock T1, T4, T16 (00, 01, 10, 11) External clock T1, T4, T16 (00, 01, 10, 11) External clock 00 16-bit timer mode 01 - - - 8-bit PPG x 1 channel 10 - - T1, T4, T16 (00, 01, 10, 11) External clock - 8-bit PWM x 1 channel 11 2 ,2 ,2 6 7 8 (01, 10, 11) - - T1, T16 , T256 (01, 10, 11) T1, T4, T16 (00, 01, 10, 11) - - 8-bit timer x 1 channel 11 Output disabled -: Don't care 91C025-112 2007-02-28 TMP91C025 (6) LCDC and MELODY/ALARM circuit supply mode This function can operate only TMRA3. It can use LCDC and MELODY/ALARM source clock TA3 clock generated by TMRA3. But this function is special mode, without low clock (XTIN, XTOUT) so keep the rule under below. Operate a. Clock generate by timer 3 b. Clock supply start (EMCCR0 STOP e. LCDC or MELODY/ALARM stop to operate f. Clock supply cut off ( 7 EMCCR0 (00E3H) Bit symbol Read/Write After reset Function 0: Off 1: On PROTECT 6 TA3LCDE 5 AHOLD R/W 0 0: Normal 1: Enable 4 TA3MLDE R/W 0 source clock. 0. 0: 32 kHz 1: TA3OUT 3 - R/W 0 2 EXTIN 1 DRVOSCH 0 DRVOSCL R 0 Protect flag R/W 0 CLK 0: 32 kHz 1: TA3OUT R/W 0 clock R/W 1 fc oscillator 1: Normal 0: Weak R/W 1 fs oscillator 1: Normal 0: Weak LCDC source Address hold Melody/Alarm Always write 1: External driver ability. driver ability. 91C025-113 2007-02-28 TMP91C025 3.8 External Memory Extension Function (MMU) This is MMU function which can expand program/data area to 104 Mbytes by having 4 local areas. Address pins to external memory are 2 extended address bus pins (EA24, EA25) or 3 extended chip select pins ( CS2A to CS2C ) in addition to 24 address bus pins (A0 to A23) which are common specification of TLCS-900 and 4 chip select pins ( CS0 to CS3 ) output from CS/WAIT controller. The feature and the recommendation setting method of two types are shown below. In addition, AH in the table is the value which number address 23 to 16 displayed as hex. Purpose Item Maximum memory size (A): For Standard Extended Memory (B): For Many Pieces Extended Memory 16 Mbytes: BANK (16 Mbytes x 1 pcs) LOCAL2 (AH = C0 to DF: 2 Mbytes x 7 BANK) Setup AH = C0 to FF to CS2 CS2 Program ROM Used local area, BANK number Setting CS/WAIT Used CS pin Maximum memory size Setup AH = 80 to FF to CS2 CS2A 64 Mbytes : BANK (64 Mbytes x 1 pcs) LOCAL3 Setup AH = 80 to BF to CS3 CS3 , EA24, EA25 32 Mbytes : BANK (16 Mbytes x 2 pcs) LOCAL3 Setup AH = 80 to FF to CS2 CS2B , CS2C Data ROM Used local area, BANK number Setting CS/WAIT Used CS pins Maximum memory size Used local area, BANK number Setting CS/WAIT Used CS pin Maximum memory size Used local area, BANK number Setting CS/WAIT Used CS pin Maximum memory size Used local area, BANK number Setting CS/WAIT Used CS pin (AH = 80 to BF: 4 Mbytes x 16 BANK) (AH = 80 to BF: 4 Mbytes x 8 BANK) 16 Mbytes: BANK (16 Mbytes x 1 pcs) LOCAL1 (AH = 40 to 5F: 2 Mbytes x 7 BANK) Setup AH = 40 to 7F to CS1 CS1 Option Program ROM 8 Mbytes: BANK (8 Mbytes x 1 pcs) LOCAL0 (AH = 10 to 1F: 1 Mbyte x 7 BANK) Setup AH = 00 to 1F to CS0 CS0 Data RAM Setup AH = 00 to 1F to CS3 CS3 2 Mbytes (2 Mbytes x 1 pcs) None Setup AH = 20 to 3F to CS0 CS0 Extended memory 1 Total memory size 16 M + 64 M + 16 M + 8 M = 104 Mbytes 16 M + 32 M + 16 M + 8 M + 2 M = 74 Mbytes 91C025-114 2007-02-28 TMP91C025 3.8.1 Recommendable Memory Map The recommendation logic address memory map at the time of varieties extension memory correspondence is shown in Figure 3.8.1. And a physical-address map is shown in Figure 3.8.2. However, when memory area is less than 16 Mbytes and is not expanded, please refer to section of CS/WAIT controller. Setting of register in MMU is not necessary. Since it is being fixed, the address of a local-area cannot be changed. BANK Address Size 000000H 1 Mbyte CS/WAIT setting CS pin Memory map COMMON0 LOCAL0 01234567 CS0 100000H 200000H CS3 CS3 1 Mbyte 2 Mbytes CS0 400000H 2 Mbytes 01234567 LOCAL1 CS1 COMMON1 012 ... 67 CS1 600000H 2 Mbytes 800000H 4 Mbytes LOCAL3 CS2 CS2B (BANK 0 to 3) CS2C (BANK 4 to 7) C00000H 2 Mbytes 01234567 LOCAL2 E00000H 2 Mbytes COMMON2 CS2 CS2A FFFF00 256 Bytes : Internal area Vector area : Overlapped with COMMON area FFFFFF Figure 3.8.1 Logical Address Map 91C025-115 2007-02-28 TMP91C025 LOCAL0 CS3 LOCAL1 CS1 LOCAL2 CS2A LOCAL3 CS2B for data RAM (8 Mbytes) 000000H BANK0 BANK1 BANK2 BANK3 BANK4 BANK5 BANK6 BANK7 800000H for option program ROM (16 Mbytes) BANK0 BANK1 BANK2 BANK3 BANK4 BANK5 BANK6 BANK7 for program ROM for data ROM (16 Mbytes) BANK0 BANK1 BANK2 BANK3 BANK4 BANK5 BANK6 BANK7 BANK3 CS2C (16 Mbytes x 2) BANK0 Internal-I/O BANK1 BANK2 1000000H 000000H Reset and interrupt vector area BANK4 BANK5 BANK6 1000000H BANK7 : Internal area : Overlapped with COMMON area Figure 3.8.2 Physical Address Map 91C025-116 2007-02-28 TMP91C025 3.8.2 Control Registers Set a bank setting value and bank enable/disable in each local register in the common area. At this time, also specify the pin function and mapping by the CS/WAIT controller. When the CPU outputs the logical address of the local area, the MMU outputs its physical address to the external address bus pin according to the value in the bank setting register. This enables access to external memory. LOCAL0 Register 7 LOCAL0 (0350H) Bit symbol Read/Write After reset Function L0E R/W 0 BANK for LOCAL0 0: Disable 1: Enable "000" setting is prohibited because it pretend COMMON 0 area 0 6 5 4 3 2 L0EA22 1 L0EA21 R/W 0 0 L0EA20 0 Setting BANK number for LOCAL0 LOCAL1 Register 7 LOCAL1 (0351H) Bit symbol Read/Write After reset Function L1E R/W 0 BANK for LOCAL1 0: Disable 1: Enable "001" setting is prohibited because it pretend COMMON 0 area 0 6 5 4 3 2 L1EA23 1 L1EA22 R/W 0 0 L1EA21 0 Setting BANK number for LOCAL1 LOCAL2 Register 7 LOCAL2 (0352H) Bit symbol Read/Write After reset Function L2E R/W 0 BANK for LOCAL2 0: Disable 1: Enable "111" setting is prohibited because it pretend COMMON 0 area 0 6 5 4 3 2 L2EA23 1 L2EA22 R/W 0 0 L2EA21 0 Setting BANK number for LOCAL2 LOCAL3 Register 7 LOCAL3 (0353H) Bit symbol Read/Write After reset Function L3E R/W 0 BANK for LOCAL3 0: Disable 1: Enable 6 5 4 - R/W 0 Always write 0. 3 L3EA25 R/W 2 L3EA24 R/W 1 L3EA23 R/W 0 0 L3EA22 R/W 0 0 0 0000~0011: CS2B 0100~0111: CS2C 1000~1111: Set prohibition Figure 3.8.3 Register of MMU 91C025-117 2007-02-28 TMP91C025 Data/Stack RAM SRAM 8 Mbytes 8 bits CS0 000000H to 1FFFFFH (Logical) 000000H to 7FFFFFH (Physical) CS0 CS1 Optional ROM FLASH 16 Mbytes 16 bits CS1 400000H to 7FFFFFH (Logical) 000000H to FFFFFFH (Physical) Data Address TMP91C025 RD , ( WR , HWR : SRAM) Program ROM MROM 16 Mbytes 16 bits CS2 CS2 C00000H to FFFFFFH (Logical) 000000H to FFFFFFH (Physical) EA24, EA25 CS3 Data ROM MROM 64 Mbytes 16 bits CS3 800000H to BFFFFFH (Logical) 0000000H to 3FFFFFFH (Physical) *In case of 16-bit bus memory TMP91C025 Control signals D [0:15] A0 A1 A2 A16 *In case of 8-bit bus memory Memory TMP91C025 Control signals D [0:7] A0 A1 A2 A7 Memory Control signals D [0:7] A0 A1 A2 A7 : : Control signals D [0:15] open A0 A1 A15 : : Figure 3.8.4 H/W Setting Example At Figure 3.8.4, it shows example of connection TMP91C025 and some memories: Program ROM: MROM, 16 Mbytes, Data ROM: MROM, 64 Mbytes, Data RAM: SRAM, 8 Mbytes, 8-bit bus, Option ROM: Flash, 16 Mbytes. In case of 16-bit bus memory connection, it need to shift 1-bit address bus from TMP91C025 and 8-bit bus case, direct connection address bus from TMP91C025. In that figure, logical address and physical address are shown. And each memory allot each chip select signal, RAM: CS0 , FLASH_ROM: CS1 , Program MROM: CS2 , Data MROM: CS3 . In case of this example, as data MROM is 64 Mbytes, this MROM connect to EA24 and EA25. Initial condition after reset, because TMP91C025 access from CS2 area, CS2 area allots to program ROM. It can set free setting except program ROM. 91C025-118 2007-02-28 TMP91C025 ;Initial Setting ;CS0 LD LD LD ;CS1 LD LD LD ;CS2 LD LD LD ;CS3 LD LD LD ;CSX LD ;Port LD to (MSAR0), 00H (MAMR0), FFH (B0CS), 89H (MSAR1), 40H (MAMR1), FFH (B1CS), 80H (MSAR2), C0H (MAMR2), 7FH (B2CS), C3H (MSAR3), 80H (MAMR3), 7FH (B3CS), 85H (BEXCS), 00H (P6FC), 3FH ; Logical address area: 000000H to 1FFFFFH ; Logical address size: 2 Mbytes ; Condition: 8-bit, 1 waits (8 Mbytes, SRAM) ; Logical address area: 400000H to 7FFFFFH ; Logical address size: 4 Mbytes ; Condition: 16-bit, 2 waits (16 Mbytes, Flash ROM) ; Logical address area: C00000H to FFFFFFH ; Logical address size: 4 Mbytes ; Condition: 16-bit, 0 waits (16 Mbytes, MROM) ; Logical address area: 800000H to BFFFFFH ; Logical address size: 4 Mbytes ; Condition: 16-bit, 3 waits (64 Mbytes, MROM) ; Other: 16-bit, 2 waits (Don't care) ; CS0 to CS3 , EA24, EA25: port 6 setting Figure 3.8.5 Bank Operation S/W Example 1 Secondly, Figure 3.8.5 shows example of initial setting at BANK operation S/W example1 of the above. Because CS0 connect to RAM: 8-bit bus, 8 Mbytes, it need to set 8-bit bus. At this example, it set 1-wait setting. In the same way CS1 set to 16-bit bus and 2 waits, CS2 set 16-bit bus and 0 waits, CS3 set 16-bit bus and 3 waits. By CS/WAIT controller, each chip selection signal's memory size, don't set actual connect memory size, need to set that logical address size: fitting to each local area. Actual physical address is set by each area's BANK register setting. CSEX setting of CS/WAIT controller is except above CS0 to CS3's setting. Finally pin condition is set. Port 60 to 65 set to CS0 , 1, 2, 3, EA24, EA25. 91C025-119 2007-02-28 TMP91C025 ;Bank Operation ;***** /CS2 ***** ORG 000000H ORG 200000H ORG 400000H ORG 600000H ORG 800000H ORG a00000H ORG c00000H ORG E00000H LD LDW LD LDW to ORG (LOCAL3), 85H HL,(800000H) (LOCAL3), 88H BC,(800000H) ; Program ROM: Start address at BANK0 of LOCAL2 ; Program ROM: Start address at BANK1 of LOCAL2 ; Program ROM: Start address at BANK2 of LOCAL2 ; Program ROM: Start address at BANK3 of LOCAL2 ; Program ROM: Start address at BANK4 of LOCAL2 ; Program ROM: Start address at BANK5 of LOCAL2 ; Program ROM: Start address at BANK6 of LOCAL2 ; Program ROM: Start address at BANK7 (= COMMON2) of LOCAL2 ; Logical address E00000H to FFFFFFH ; Physical address 0E00000H to 0FFFFFFH ; LOCAL3 BANK5 set 14xxxxH ; Load data (5555H) form BANK5 (140000H: Physical address) of LOCAL3 ( CS3 ) ; LOCAL3 BANK8 set 20xxxxH ; Load data (AAAAH) form BANK8 (200000H: Physical address) of LOCAL3 ( CS3 ) ; Program ROM: End address at BANK7 (= COMMON2) of LOCAL2 FFFFFFH ;***** /CS3 ***** ORG 0000000H ORG 0400000H ORG 0800000H ORG 0C00000H ORG 1000000H ORG 1400000H dw 5555H to ORG 1800000H ORG 1C00000H ORG 2000000H dw AAAAH to ORG 2400000H ORG 2800000H ORG 2C00000H ORG 3000000H ORG 3400000H ORG 3800000H ORG 3C00000H ORG 3FFFFFFH ; Data ROM: Start address at BANK0 of LOCAL3 ; Data ROM: Start address at BANK1 of LOCAL3 ; Data ROM: Start address at BANK2 of LOCAL3 ; Data ROM: Start address at BANK3 of LOCAL3 ; Data ROM: Start address at BANK4 of LOCAL3 ; Data ROM: Start address at BANK5 of LOCAL3 ; Data ROM: Start address at BANK6 of LOCAL3 ; Data ROM: Start address at BANK7 of LOCAL3 ; Data ROM: Start address at BANK8 of LOCAL3 ; Data ROM: Start address at BANK9 of LOCAL3 ; Data ROM: Start address at BANK10 of LOCAL3 ; Data ROM: Start address at BANK11 of LOCAL3 ; Data ROM: Start address at BANK12 of LOCAL3 ; Data ROM: Start address at BANK13 of LOCAL3 ; Data ROM: Start address at BANK14 of LOCAL3 ; Data ROM: Start address at BANK15 of LOCAL3 ; Data ROM: End address at BANK15 of LOCAL3 Figure 3.8.6 Bank Operation S/W Example 2 Figure 3.8.6 shows example of data access between one BANK and other BANK is one software example. A dot line square area shows one memory and each dot line square shows CS2 's program ROM and CS3 's data ROM. Program start from E00000H address, firstly, write to BANK register of LOCAL3 area upper 5-bit address of access point. In case of this TMP91C025, because most upper address bit of physical address is EA25, most upper address bit of BANK register is meaningless. 4 bits of upper 5-bit address means 16 BANKs. After setting BANK5, accessing 800000H to BFFFFFH address: Logical local3 address, actually access to physical 1400000H to 1700000H address. 91C025-120 2007-02-28 TMP91C025 ;Bank Operation ;***** /CS2 ***** ORG 000000H ORG 200000H NOP to JP E00100H ORG 400000H ORG 600000H NOP to JP E00200H ORG 800000H ORG a00000H ORG c00000H !!!! Program Start !!!! ORG E00000H ; Program ROM: Start address at BANK0 of LOCAL2 ; Program ROM: Start address at BANK1 of LOCAL2 ; Operation at BANK1of LOCAL2 ; Jump to BANK7 (= COMMON2) of LOCAL2 ; Program ROM: Start address at BANK2 of LOCAL2 ; Program ROM: Start address at BANK3 of LOCAL2 ; Operation at BANK3 of LOCAL2 ; Jump to BANK7 (= COMMON2) of LOCAL2 ; Program ROM: Start address at BANK4 of LOCAL2 ; Program ROM: Start address at BANK5 of LOCAL2 ; Program ROM: Start address at BANK6 of LOCAL2 LD JP to ORG (LOCAL2), 81H C00000H ; Program ROM: Start address at BANK7 (= COMMON2) of LOCAL2 ; Logical address E00000H to FFFFFFH ; Physical address 0E00000H to 0FFFFFFH ; LOCAL2 BANK1 set 20xxxxH ; Jump to BANK1 (200000H: Physical address) of LOCAL2 E00100H LD (LOCAL2), 83H JP C00000H E00200H LD (LOCAL1),84H JP 400000H FFFFFFH ; LOCAL2 BANK3 set 60xxxxH ; Jump to BANK3 (600000H: Physical address) of LOCAL2 to ORG ORG ; LOCAL1 BANK4 set 80xxxxH ; Jump to BANK4 (800000H: Physical address) of LOCAL1 ; Program ROM: End address at BANK7(= COMMON2) of LOCAL2 ;***** /CS1 ***** ORG 000000H ORG 200000H ORG 400000H ORG 600000H LD JP ORG 800000H NOP to JP ORG a00000H ORG c00000H ORG E00000H LD JP (LOCAL1),87H 400000H ; Program ROM: Start address at BANK0 of LOCAL1 ; Program ROM: Start address at BANK1 of LOCAL1 ; Program ROM: Start address at BANK2 of LOCAL1 ; Program ROM: Start address at BANK3 (= COMMON1) of LOCAL1 ; LOCAL1 BANK7 set E0xxxxH ; Jump to BANK7 (E00000H: Physical address) of LOCAL1 ; Program ROM: Start address at BANK4 of LOCAL1 ; Operation at BANK4 of LOCAL1 ; Jump to BANK3 (= COMMON1) of LOCAL1 ; Program ROM: Start address at BANK5 of LOCAL1 ; Program ROM: Start address at BANK6 of LOCAL1 ; Program ROM: Start address at BANK7 of LOCAL1 ; LOCAL1 BANK0 set 00xxxxH ; Jump to BANK0 (000000H: Physical address) of LOCAL1 600000H (LOCAL1),80H 400000H It's prohibiting to set other BANK setting in except common area Program run away. ORG FFFFFFH ; Program ROM: End address at BANK7 of LOCAL1 Figure 3.8.7 Bank Operation S/W Example 3 91C025-121 2007-02-28 TMP91C025 At bank operation S/W Example 3 of the above, Figure 3.8.7 shows example of program jump. In the same way with before example, two dot line squares show each CS2 's program ROM and CS1 's option ROM. Program start from E00000H common address, firstly, write to BANK register of LOCAL2 area upper 3-bit address of jumping point. After setting BANK1, jumping C00000H to DFFFFFH address: logical local2 address, actually jump to physical 2000000H to 3FFFFFH address. When return to common area, it can only jump to E00000H to FFFFFFH without writing to BANK register of LOCAL2 area. By a way of setting of BANK register, the setting that BANK address and common address conflict with is possible. When two kinds or more logical addresses to show common area exist, management of BANK is confused. We recommends not using the BANK setting, BANK address and common address conflict with. When it jumps to one memory from other different memory, it can set same as the last time setting. It needs to write to BANK register of LOCAL1 area upper 3-bit address of jumping point. After setting BANK4, jumping 400000H to 5FFFFFH address: logical local1 address, actually jump to physical 8000000H to 9FFFFFH address. It is a mark paid attention to here, it needs to go by way of common area by all means when moves from a bank to a bank. In other words, it must write to BANK register only in common area and it is prohibit writing the BANK register in BANK area. If it modify the BANK register's data in BANK area, program runaway. 91C025-122 2007-02-28 TMP91C025 3.9 Serial Channels TMP91C025 includes 2 serial I/O channels. For both channels either UART mode (Asynchronous transmission) or I/O Interface mode (Synchronous transmission) can be selected. * I/O interface mode * UART mode Mode 0: Mode 1: Mode 2: Mode 3: For transmitting and receiving I/O data using the synchronizing signal SCLK for extending I/O. 7-bit data 8-bit data 9-bit data In mode 1 and mode 2 a parity bit can be added. mode 3 has a wakeup function for making the master controller start slave controllers via a serial link (A multi-controller system). Figure 3.9.2, Figure 3.9.3 are block diagrams for each channel. Serial channels 0 and 1 can be used independently. Both channels operate in the same fashion except for the following points; hence only the operation of channel 0 is explained below. Table 3.9.1 Differences between Channels 0 to 1 Channel 0 Pin name TXD0 (PC0) RXD0 (PC1) CTS0 /SCLK0 (PC2) IrDA mode Yes Channel 1 TXD1 (PC3) RXD1 (PC4) CTS1 /SCLK1 (PC5) No This chapter contains the following sections: 3.9.1 3.9.2 3.9.3 3.9.4 3.9.5 Block Diagrams Operation of Each Circuit SFRs Operation in Each Mode Support for IrDA 91C025-123 2007-02-28 TMP91C025 * Mode 0 (I/O interface mode) Bit0 1 2 3 4 5 6 7 Transfer direction * Mode 1 (7-bit UART mode) No parity Start Bit0 1 2 3 4 5 6 Stop Parity Start Bit0 1 2 3 4 5 6 Parity Stop * Mode 2 (8-bit UART mode) No parity Start Bit0 1 2 3 4 5 6 7 Stop Parity Start Bit0 1 2 3 4 5 6 7 Parity Stop * Mode 3 (9-bit UART mode) Start Bit0 1 2 3 4 5 6 7 8 Stop Wake up Start Bit0 1 2 3 4 5 6 7 Bit8 Stop When bit8 = 1, address (Select code) is denoted. When bit8 = 0, data is denoted. Figure 3.9.1 Data Formats 91C025-124 2007-02-28 TMP91C025 3.9.1 Block Diagrams Figure 3.9.2 is a block diagram representing serial channel 0. Prescaler T0 2 4 8 16 32 64 T2 T8 T32 Serial clock generation circuit BR0CR T0 T2 T8 T32 Prescaler Selector SIOCLK /2 SCLK0 Concurrent with PC2 I/O interface mode Selector fSYS BR0CR SC0MOD0 SC0MOD0 I/O interface mode SC0CR (UART only / 16) SCLK0 Concurrent with PC2 (UART only / 16) Receive counter Transmision counter RXDCLK SC0MOD0 Parity control Transmission control SC0MOD0 CTS0 Concurrent with PC2 RXD0 Concurrent with PC1 RB8 Receive buffer 1 (Shift register) Receive buffer 2 (SC0BUF) Error flag TB8 Transmission buffer (SC0BUF) SC0CR TXD0 Concurrent with PC0 Figure 3.9.2 Block Diagram of the Serial Channel 0 (SIO0) 91C025-125 2007-02-28 TMP91C025 Prescaler T0 2 4 8 16 32 64 T2 T8 T32 Serial clock generation circuit BR1CR T0 T2 T8 T32 Prescaler Selector Selector Selector UART mode SIOCLK /2 SCLK1 Concurrent with PC5 I/O interface mode Selector fSYS BR1CR SC1MOD0 SC1MOD0 I/O interface mode SC1CR |